system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-07-21 10:24:33 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

hw/usb: extract sysbus-ohci to a separate file

Browse source 
Split the sysbus version to a separate file so that it is not
included in PCI-only machines, and adjust Kconfig for machines
that do need sysbus-ohci.  The copyrights are based on the
time and employer of balrog and Paul Brook's contributions.

While adjusting the SM501 dependency, move it to the right place
instead of keeping it in the R4D machine.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240223124406.234509-10-pbonzini@redhat.com>
[PMD: Rename some functions using 'ohci_sysbus_' prefix]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Paolo Bonzini 2024-02-23 13:44:05 +01:00 committed by Philippe Mathieu-Daudé
parent ccced963c5
commit 15f07fb821
8 changed files with 102 additions and 65 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
hw/arm/Kconfig
View file

@ -185,7 +185,7 @@ config PXA2XX
select SERIAL
select SD
select SSI
select USB_OHCI
select USB_OHCI_SYSBUS
select PCMCIA
config GUMSTIX
@ -256,7 +256,7 @@ config REALVIEW
select PL310 # cache controller
select ARM_SBCON_I2C
select DS1338 # I2C RTC+NVRAM
select USB_OHCI
select USB_OHCI_SYSBUS
config SBSA_REF
bool
@ -339,7 +339,7 @@ config VERSATILE
select PL080 # DMA controller
select PL190 # Vector PIC
select REALVIEW
select USB_OHCI
select USB_OHCI_SYSBUS
config VEXPRESS
bool
@ -395,6 +395,7 @@ config ALLWINNER_A10
select AXP2XX_PMU
select SERIAL
select UNIMP
select USB_OHCI_SYSBUS
config ALLWINNER_H3
bool
@ -408,7 +409,7 @@ config ALLWINNER_H3
select ARM_TIMER
select ARM_GIC
select UNIMP
select USB_OHCI
select USB_OHCI_SYSBUS
select USB_EHCI_SYSBUS
select SD
@ -424,7 +425,7 @@ config ALLWINNER_R40
select ARM_TIMER
select ARM_GIC
select UNIMP
select USB_OHCI
select USB_OHCI_SYSBUS
select USB_EHCI_SYSBUS
select SD
@ -530,6 +531,7 @@ config NPCM7XX
select SSI
select UNIMP
select PCA954X
select USB_OHCI_SYSBUS
config FSL_IMX25
bool

1
hw/display/Kconfig
View file

@ -77,6 +77,7 @@ config SM501
select I2C
select DDC
select SERIAL
select USB_OHCI_SYSBUS
config TCX
bool

2
hw/ppc/Kconfig
View file

@ -70,7 +70,7 @@ config SAM460EX
select SM501
select SMBUS_EEPROM
select USB_EHCI_SYSBUS
select USB_OHCI
select USB_OHCI_SYSBUS
select FDT_PPC
config AMIGAONE

1
hw/sh4/Kconfig
View file

@ -6,7 +6,6 @@ config R2D
select I82378 if TEST_DEVICES
select IDE_MMIO
select PFLASH_CFI02
select USB_OHCI_PCI
select PCI
select SM501
select SH7750

4
hw/usb/Kconfig
View file

@ -11,6 +11,10 @@ config USB_OHCI
bool
select USB
config USB_OHCI_SYSBUS
bool
select USB_OHCI
config USB_OHCI_PCI
bool
default y if PCI_DEVICES

88
hw/usb/hcd-ohci-sysbus.c Normal file
View file

@ -0,0 +1,88 @@
/*
* QEMU USB OHCI Emulation
* Copyright (c) 2006 Openedhand Ltd.
* Copyright (c) 2010 CodeSourcery
* Copyright (c) 2024 Red Hat, Inc.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "hw/usb.h"
#include "migration/vmstate.h"
#include "hw/sysbus.h"
#include "hw/qdev-dma.h"
#include "hw/qdev-properties.h"
#include "trace.h"
#include "hcd-ohci.h"
static void ohci_sysbus_realize(DeviceState *dev, Error **errp)
{
OHCISysBusState *s = SYSBUS_OHCI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Error *err = NULL;
usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset,
s->masterbus, s->firstport,
&address_space_memory, ohci_sysbus_die, &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_init_irq(sbd, &s->ohci.irq);
sysbus_init_mmio(sbd, &s->ohci.mem);
}
static void ohci_sysbus_reset(DeviceState *dev)
{
OHCISysBusState *s = SYSBUS_OHCI(dev);
OHCIState *ohci = &s->ohci;
ohci_hard_reset(ohci);
}
static Property ohci_sysbus_properties[] = {
DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus),
DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0),
DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void ohci_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = ohci_sysbus_realize;
set_bit(DEVICE_CATEGORY_USB, dc->categories);
dc->desc = "OHCI USB Controller";
device_class_set_props(dc, ohci_sysbus_properties);
dc->reset = ohci_sysbus_reset;
}
static const TypeInfo ohci_sysbus_types[] = {
{
.name = TYPE_SYSBUS_OHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(OHCISysBusState),
.class_init = ohci_sysbus_class_init,
},
};
DEFINE_TYPES(ohci_sysbus_types);

58
hw/usb/hcd-ohci.c
View file

@ -1955,31 +1955,6 @@ void ohci_sysbus_die(struct OHCIState *ohci)
ohci_bus_stop(ohci);
}
static void ohci_realize_pxa(DeviceState *dev, Error **errp)
{
OHCISysBusState *s = SYSBUS_OHCI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Error *err = NULL;
usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset,
s->masterbus, s->firstport,
&address_space_memory, ohci_sysbus_die, &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_init_irq(sbd, &s->ohci.irq);
sysbus_init_mmio(sbd, &s->ohci.mem);
}
static void usb_ohci_reset_sysbus(DeviceState *dev)
{
OHCISysBusState *s = SYSBUS_OHCI(dev);
OHCIState *ohci = &s->ohci;
ohci_hard_reset(ohci);
}
static const VMStateDescription vmstate_ohci_state_port = {
.name = "ohci-core/port",
.version_id = 1,
@ -2054,36 +2029,3 @@ const VMStateDescription vmstate_ohci_state = {
NULL
}
};
static Property ohci_sysbus_properties[] = {
DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus),
DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0),
DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void ohci_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = ohci_realize_pxa;
set_bit(DEVICE_CATEGORY_USB, dc->categories);
dc->desc = "OHCI USB Controller";
device_class_set_props(dc, ohci_sysbus_properties);
dc->reset = usb_ohci_reset_sysbus;
}
static const TypeInfo ohci_sysbus_info = {
.name = TYPE_SYSBUS_OHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(OHCISysBusState),
.class_init = ohci_sysbus_class_init,
};
static void ohci_register_types(void)
{
type_register_static(&ohci_sysbus_info);
}
type_init(ohci_register_types)

1
hw/usb/meson.build
View file

@ -15,6 +15,7 @@ system_ss.add(when: 'CONFIG_USB', if_true: files(
system_ss.add(when: 'CONFIG_USB_UHCI', if_true: files('hcd-uhci.c'))
system_ss.add(when: 'CONFIG_USB_OHCI', if_true: files('hcd-ohci.c'))
system_ss.add(when: 'CONFIG_USB_OHCI_PCI', if_true: files('hcd-ohci-pci.c'))
system_ss.add(when: 'CONFIG_USB_OHCI_SYSBUS', if_true: files('hcd-ohci-sysbus.c'))
system_ss.add(when: 'CONFIG_USB_EHCI', if_true: files('hcd-ehci.c'))
system_ss.add(when: 'CONFIG_USB_EHCI_PCI', if_true: files('hcd-ehci-pci.c'))
system_ss.add(when: 'CONFIG_USB_EHCI_SYSBUS', if_true: files('hcd-ehci.c', 'hcd-ehci-sysbus.c'))