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sifive_u: Rename memmap enum constants
Some of the enum constant names conflict with the QOM type check macros (SIFIVE_U_OTP, SIFIVE_U_PRCI). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200911173447.165713-3-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Eduardo Habkost
parent
5488f2760a
commit
13b8c35418
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@ -70,23 +70,23 @@ static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} sifive_u_memmap[] = {
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[SIFIVE_U_DEBUG] = { 0x0, 0x100 },
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[SIFIVE_U_MROM] = { 0x1000, 0xf000 },
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[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
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[SIFIVE_U_L2CC] = { 0x2010000, 0x1000 },
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[SIFIVE_U_PDMA] = { 0x3000000, 0x100000 },
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[SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
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[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
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[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
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[SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
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[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
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[SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
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[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
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[SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
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[SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
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[SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
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[SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
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[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
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[SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
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[SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
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[SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
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[SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
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[SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
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[SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
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[SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
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[SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
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[SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
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[SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
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[SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
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[SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
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[SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
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[SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
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[SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
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[SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
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[SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
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};
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#define OTP_SERIAL 1
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@ -145,10 +145,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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g_free(nodename);
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nodename = g_strdup_printf("/memory@%lx",
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(long)memmap[SIFIVE_U_DRAM].base);
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(long)memmap[SIFIVE_U_DEV_DRAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
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memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
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mem_size >> 32, mem_size);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
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g_free(nodename);
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@ -203,39 +203,39 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/clint@%lx",
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(long)memmap[SIFIVE_U_CLINT].base);
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(long)memmap[SIFIVE_U_DEV_CLINT].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_CLINT].base,
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0x0, memmap[SIFIVE_U_CLINT].size);
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0x0, memmap[SIFIVE_U_DEV_CLINT].base,
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0x0, memmap[SIFIVE_U_DEV_CLINT].size);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, ms->smp.cpus * sizeof(uint32_t) * 4);
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g_free(cells);
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g_free(nodename);
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nodename = g_strdup_printf("/soc/otp@%lx",
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(long)memmap[SIFIVE_U_OTP].base);
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(long)memmap[SIFIVE_U_DEV_OTP].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_OTP].base,
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0x0, memmap[SIFIVE_U_OTP].size);
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0x0, memmap[SIFIVE_U_DEV_OTP].base,
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0x0, memmap[SIFIVE_U_DEV_OTP].size);
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qemu_fdt_setprop_string(fdt, nodename, "compatible",
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"sifive,fu540-c000-otp");
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g_free(nodename);
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prci_phandle = phandle++;
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nodename = g_strdup_printf("/soc/clock-controller@%lx",
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(long)memmap[SIFIVE_U_PRCI].base);
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(long)memmap[SIFIVE_U_DEV_PRCI].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
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qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
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qemu_fdt_setprop_cells(fdt, nodename, "clocks",
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hfclk_phandle, rtcclk_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_PRCI].base,
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0x0, memmap[SIFIVE_U_PRCI].size);
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0x0, memmap[SIFIVE_U_DEV_PRCI].base,
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0x0, memmap[SIFIVE_U_DEV_PRCI].size);
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qemu_fdt_setprop_string(fdt, nodename, "compatible",
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"sifive,fu540-c000-prci");
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g_free(nodename);
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@ -259,7 +259,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
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(long)memmap[SIFIVE_U_PLIC].base);
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(long)memmap[SIFIVE_U_DEV_PLIC].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
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@ -267,8 +267,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_PLIC].base,
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0x0, memmap[SIFIVE_U_PLIC].size);
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0x0, memmap[SIFIVE_U_DEV_PLIC].base,
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0x0, memmap[SIFIVE_U_DEV_PLIC].size);
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qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
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plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
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@ -277,7 +277,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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gpio_phandle = phandle++;
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nodename = g_strdup_printf("/soc/gpio@%lx",
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(long)memmap[SIFIVE_U_GPIO].base);
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(long)memmap[SIFIVE_U_DEV_GPIO].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "clocks",
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@ -287,8 +287,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
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qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_GPIO].base,
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0x0, memmap[SIFIVE_U_GPIO].size);
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0x0, memmap[SIFIVE_U_DEV_GPIO].base,
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0x0, memmap[SIFIVE_U_DEV_GPIO].size);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
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SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
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SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
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@ -306,7 +306,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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g_free(nodename);
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nodename = g_strdup_printf("/soc/dma@%lx",
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(long)memmap[SIFIVE_U_PDMA].base);
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(long)memmap[SIFIVE_U_DEV_PDMA].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
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@ -315,18 +315,18 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_PDMA].base,
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0x0, memmap[SIFIVE_U_PDMA].size);
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0x0, memmap[SIFIVE_U_DEV_PDMA].base,
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0x0, memmap[SIFIVE_U_DEV_PDMA].size);
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qemu_fdt_setprop_string(fdt, nodename, "compatible",
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"sifive,fu540-c000-pdma");
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g_free(nodename);
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nodename = g_strdup_printf("/soc/cache-controller@%lx",
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(long)memmap[SIFIVE_U_L2CC].base);
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(long)memmap[SIFIVE_U_DEV_L2CC].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_L2CC].base,
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0x0, memmap[SIFIVE_U_L2CC].size);
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0x0, memmap[SIFIVE_U_DEV_L2CC].base,
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0x0, memmap[SIFIVE_U_DEV_L2CC].size);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
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SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
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@ -341,15 +341,15 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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phy_phandle = phandle++;
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nodename = g_strdup_printf("/soc/ethernet@%lx",
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(long)memmap[SIFIVE_U_GEM].base);
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(long)memmap[SIFIVE_U_DEV_GEM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible",
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"sifive,fu540-c000-gem");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_GEM].base,
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0x0, memmap[SIFIVE_U_GEM].size,
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0x0, memmap[SIFIVE_U_GEM_MGMT].base,
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0x0, memmap[SIFIVE_U_GEM_MGMT].size);
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0x0, memmap[SIFIVE_U_DEV_GEM].base,
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0x0, memmap[SIFIVE_U_DEV_GEM].size,
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0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
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0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
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qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
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qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
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qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
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@ -370,19 +370,19 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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g_free(nodename);
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nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
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(long)memmap[SIFIVE_U_GEM].base);
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(long)memmap[SIFIVE_U_DEV_GEM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
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qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
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g_free(nodename);
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nodename = g_strdup_printf("/soc/serial@%lx",
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(long)memmap[SIFIVE_U_UART0].base);
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(long)memmap[SIFIVE_U_DEV_UART0].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_UART0].base,
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0x0, memmap[SIFIVE_U_UART0].size);
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0x0, memmap[SIFIVE_U_DEV_UART0].base,
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0x0, memmap[SIFIVE_U_DEV_UART0].size);
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qemu_fdt_setprop_cells(fdt, nodename, "clocks",
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prci_phandle, PRCI_CLK_TLCLK);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
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@ -414,7 +414,7 @@ static void sifive_u_machine_init(MachineState *machine)
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *flash0 = g_new(MemoryRegion, 1);
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target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
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target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
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uint32_t start_addr_hi32 = 0x00000000;
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int i;
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uint32_t fdt_load_addr;
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@ -429,13 +429,13 @@ static void sifive_u_machine_init(MachineState *machine)
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/* register RAM */
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memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
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memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
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main_mem);
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/* register QSPI0 Flash */
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memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
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memmap[SIFIVE_U_FLASH0].size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
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memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
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flash0);
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/* register gpio-restart */
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@ -461,14 +461,14 @@ static void sifive_u_machine_init(MachineState *machine)
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switch (s->msel) {
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case MSEL_MEMMAP_QSPI0_FLASH:
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start_addr = memmap[SIFIVE_U_FLASH0].base;
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start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
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break;
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case MSEL_L2LIM_QSPI0_FLASH:
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case MSEL_L2LIM_QSPI2_SD:
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start_addr = memmap[SIFIVE_U_L2LIM].base;
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start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
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break;
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default:
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start_addr = memmap[SIFIVE_U_DRAM].base;
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start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
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break;
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}
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@ -496,7 +496,7 @@ static void sifive_u_machine_init(MachineState *machine)
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}
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/* Compute the fdt load address in dram */
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fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
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fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
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machine->ram_size, s->fdt);
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#if defined(TARGET_RISCV64)
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start_addr_hi32 = start_addr >> 32;
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@ -528,10 +528,10 @@ static void sifive_u_machine_init(MachineState *machine)
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reset_vec[i] = cpu_to_le32(reset_vec[i]);
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}
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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memmap[SIFIVE_U_MROM].base, &address_space_memory);
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memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
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riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
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memmap[SIFIVE_U_MROM].size,
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riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
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memmap[SIFIVE_U_DEV_MROM].size,
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sizeof(reset_vec), kernel_entry);
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}
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@ -674,8 +674,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
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/* boot rom */
|
||||
memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
|
||||
memmap[SIFIVE_U_MROM].size, &error_fatal);
|
||||
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
|
||||
memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
|
||||
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
|
||||
mask_rom);
|
||||
|
||||
/*
|
||||
|
|
@ -688,8 +688,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
|
|||
* too generous to misbehaving guests.
|
||||
*/
|
||||
memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
|
||||
memmap[SIFIVE_U_L2LIM].size, &error_fatal);
|
||||
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
|
||||
memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
|
||||
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
|
||||
l2lim_mem);
|
||||
|
||||
/* create PLIC hart topology configuration string */
|
||||
|
|
@ -707,7 +707,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
|
|||
}
|
||||
|
||||
/* MMIO */
|
||||
s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
|
||||
s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
|
||||
plic_hart_config, 0,
|
||||
SIFIVE_U_PLIC_NUM_SOURCES,
|
||||
SIFIVE_U_PLIC_NUM_PRIORITIES,
|
||||
|
|
@ -717,27 +717,27 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
|
|||
SIFIVE_U_PLIC_ENABLE_STRIDE,
|
||||
SIFIVE_U_PLIC_CONTEXT_BASE,
|
||||
SIFIVE_U_PLIC_CONTEXT_STRIDE,
|
||||
memmap[SIFIVE_U_PLIC].size);
|
||||
memmap[SIFIVE_U_DEV_PLIC].size);
|
||||
g_free(plic_hart_config);
|
||||
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
|
||||
sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
|
||||
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
|
||||
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
|
||||
sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
|
||||
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
|
||||
sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
|
||||
memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
|
||||
sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
|
||||
memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
|
||||
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
|
||||
SIFIVE_CLINT_TIMEBASE_FREQ, false);
|
||||
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
|
||||
return;
|
||||
}
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
|
||||
|
||||
qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
|
||||
return;
|
||||
}
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
|
||||
|
||||
/* Pass all GPIOs to the SOC layer so they are available to the board */
|
||||
qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
|
||||
|
|
@ -751,7 +751,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
|
|||
|
||||
/* PDMA */
|
||||
sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
|
||||
|
||||
/* Connect PDMA interrupts to the PLIC */
|
||||
for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
|
||||
|
|
@ -764,7 +764,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
|
|||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
|
||||
return;
|
||||
}
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
|
||||
|
||||
/* FIXME use qdev NIC properties instead of nd_table[] */
|
||||
if (nd->used) {
|
||||
|
|
@ -776,18 +776,18 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
|
|||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
|
||||
return;
|
||||
}
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
|
||||
qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
|
||||
|
||||
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
|
||||
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
|
||||
memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
|
||||
|
||||
create_unimplemented_device("riscv.sifive.u.dmc",
|
||||
memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
|
||||
memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
|
||||
|
||||
create_unimplemented_device("riscv.sifive.u.l2cc",
|
||||
memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size);
|
||||
memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
|
||||
}
|
||||
|
||||
static Property sifive_u_soc_props[] = {
|
||||
|
|
|
|||
|
|
@ -70,23 +70,23 @@ typedef struct SiFiveUState {
|
|||
} SiFiveUState;
|
||||
|
||||
enum {
|
||||
SIFIVE_U_DEBUG,
|
||||
SIFIVE_U_MROM,
|
||||
SIFIVE_U_CLINT,
|
||||
SIFIVE_U_L2CC,
|
||||
SIFIVE_U_PDMA,
|
||||
SIFIVE_U_L2LIM,
|
||||
SIFIVE_U_PLIC,
|
||||
SIFIVE_U_PRCI,
|
||||
SIFIVE_U_UART0,
|
||||
SIFIVE_U_UART1,
|
||||
SIFIVE_U_GPIO,
|
||||
SIFIVE_U_OTP,
|
||||
SIFIVE_U_DMC,
|
||||
SIFIVE_U_FLASH0,
|
||||
SIFIVE_U_DRAM,
|
||||
SIFIVE_U_GEM,
|
||||
SIFIVE_U_GEM_MGMT
|
||||
SIFIVE_U_DEV_DEBUG,
|
||||
SIFIVE_U_DEV_MROM,
|
||||
SIFIVE_U_DEV_CLINT,
|
||||
SIFIVE_U_DEV_L2CC,
|
||||
SIFIVE_U_DEV_PDMA,
|
||||
SIFIVE_U_DEV_L2LIM,
|
||||
SIFIVE_U_DEV_PLIC,
|
||||
SIFIVE_U_DEV_PRCI,
|
||||
SIFIVE_U_DEV_UART0,
|
||||
SIFIVE_U_DEV_UART1,
|
||||
SIFIVE_U_DEV_GPIO,
|
||||
SIFIVE_U_DEV_OTP,
|
||||
SIFIVE_U_DEV_DMC,
|
||||
SIFIVE_U_DEV_FLASH0,
|
||||
SIFIVE_U_DEV_DRAM,
|
||||
SIFIVE_U_DEV_GEM,
|
||||
SIFIVE_U_DEV_GEM_MGMT
|
||||
};
|
||||
|
||||
enum {
|
||||
|
|
|
|||
Loading…
Reference in a new issue