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hw/sparc: Allow building without the leon3 machine
When building without the leon3 machine, we get this link failure: /usr/bin/ld: target_sparc_int32_helper.c.o: in function `leon3_irq_manager': target/sparc/int32_helper.c:172: undefined reference to `leon3_irq_ack' This is because the leon3_irq_ack() is declared in hw/sparc/leon3.c, which is only build when CONFIG_LEON3 is selected. Fix by moving the leon3_cache_control_int() / leon3_irq_manager() (which are specific to the leon3 machine) to hw/sparc/leon3.c. Move the trace events along (but don't rename them). leon3_irq_ack() is now locally used, declare it static to reduce its scope. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> Tested-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20210428141655.387430-2-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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@ -137,7 +137,36 @@ static void main_cpu_reset(void *opaque)
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env->regbase[6] = s->sp;
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}
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void leon3_irq_ack(void *irq_manager, int intno)
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static void leon3_cache_control_int(CPUSPARCState *env)
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{
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uint32_t state = 0;
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if (env->cache_control & CACHE_CTRL_IF) {
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/* Instruction cache state */
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state = env->cache_control & CACHE_STATE_MASK;
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if (state == CACHE_ENABLED) {
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state = CACHE_FROZEN;
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trace_int_helper_icache_freeze();
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}
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env->cache_control &= ~CACHE_STATE_MASK;
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env->cache_control |= state;
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}
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if (env->cache_control & CACHE_CTRL_DF) {
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/* Data cache state */
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state = (env->cache_control >> 2) & CACHE_STATE_MASK;
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if (state == CACHE_ENABLED) {
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state = CACHE_FROZEN;
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trace_int_helper_dcache_freeze();
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}
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env->cache_control &= ~(CACHE_STATE_MASK << 2);
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env->cache_control |= (state << 2);
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}
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}
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static void leon3_irq_ack(void *irq_manager, int intno)
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{
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grlib_irqmp_ack((DeviceState *)irq_manager, intno);
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}
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@ -181,6 +210,12 @@ static void leon3_set_pil_in(void *opaque, int n, int level)
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}
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}
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static void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
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{
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leon3_irq_ack(irq_manager, intno);
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leon3_cache_control_int(env);
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}
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static void leon3_generic_hw_init(MachineState *machine)
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{
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ram_addr_t ram_size = machine->ram_size;
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@ -19,3 +19,5 @@ sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64
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# leon3.c
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leon3_set_irq(int intno) "Set CPU IRQ %d"
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leon3_reset_irq(int intno) "Reset CPU IRQ %d"
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int_helper_icache_freeze(void) "Instruction cache: freeze"
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int_helper_dcache_freeze(void) "Data cache: freeze"
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@ -615,15 +615,9 @@ int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
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int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
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void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
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/* int_helper.c */
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void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
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/* sun4m.c, sun4u.c */
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void cpu_check_irqs(CPUSPARCState *env);
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/* leon3.c */
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void leon3_irq_ack(void *irq_manager, int intno);
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#if defined (TARGET_SPARC64)
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static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
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@ -136,40 +136,3 @@ void sparc_cpu_do_interrupt(CPUState *cs)
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}
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#endif
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}
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#if !defined(CONFIG_USER_ONLY)
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static void leon3_cache_control_int(CPUSPARCState *env)
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{
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uint32_t state = 0;
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if (env->cache_control & CACHE_CTRL_IF) {
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/* Instruction cache state */
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state = env->cache_control & CACHE_STATE_MASK;
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if (state == CACHE_ENABLED) {
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state = CACHE_FROZEN;
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trace_int_helper_icache_freeze();
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}
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env->cache_control &= ~CACHE_STATE_MASK;
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env->cache_control |= state;
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}
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if (env->cache_control & CACHE_CTRL_DF) {
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/* Data cache state */
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state = (env->cache_control >> 2) & CACHE_STATE_MASK;
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if (state == CACHE_ENABLED) {
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state = CACHE_FROZEN;
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trace_int_helper_dcache_freeze();
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}
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env->cache_control &= ~(CACHE_STATE_MASK << 2);
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env->cache_control |= (state << 2);
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}
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}
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void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
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{
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leon3_irq_ack(irq_manager, intno);
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leon3_cache_control_int(env);
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}
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#endif
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@ -15,10 +15,6 @@ int_helper_set_softint(uint32_t softint) "new 0x%08x"
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int_helper_clear_softint(uint32_t softint) "new 0x%08x"
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int_helper_write_softint(uint32_t softint) "new 0x%08x"
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# int32_helper.c
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int_helper_icache_freeze(void) "Instruction cache: freeze"
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int_helper_dcache_freeze(void) "Data cache: freeze"
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# win_helper.c
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win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=0x%x"
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win_helper_switch_pstate(uint32_t pstate_regs, uint32_t new_pstate_regs) "change_pstate: switching regs old=0x%x new=0x%x"
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