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target/openrisc: Cache constant 0 in DisasContext
We are virtually certain to have fetched constant 0 once, at the beginning of the TB, so we might as well use it elsewhere. Reviewed-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -52,6 +52,8 @@ typedef struct DisasContext {
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/* The temporary corresponding to register 0 for this compilation. */
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TCGv R0;
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/* The constant zero. */
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TCGv zero;
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} DisasContext;
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static inline bool is_user(DisasContext *dc)
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@ -536,10 +538,8 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a)
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static bool trans_l_cmov(DisasContext *dc, arg_dab *a)
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{
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TCGv zero = tcg_constant_tl(0);
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check_r0_write(dc, a->d);
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tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, zero,
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tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, dc->zero,
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cpu_R(dc, a->a), cpu_R(dc, a->b));
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return true;
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}
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@ -630,9 +630,8 @@ static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond)
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target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
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TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8);
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TCGv t_true = tcg_constant_tl(tmp_pc);
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TCGv t_zero = tcg_constant_tl(0);
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tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next);
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tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, dc->zero, t_true, t_next);
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dc->delayed_branch = 2;
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}
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@ -1594,8 +1593,9 @@ static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs)
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/* Allow the TCG optimizer to see that R0 == 0,
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when it's true, which is the common case. */
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dc->zero = tcg_constant_tl(0);
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if (dc->tb_flags & TB_FLAGS_R0_0) {
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dc->R0 = tcg_constant_tl(0);
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dc->R0 = dc->zero;
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} else {
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dc->R0 = cpu_regs[0];
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}
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