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hw/riscv/virt-acpi-build.c: Add AIA support in RINTC

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Update the RINTC structure in MADT with AIA related fields.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-6-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Sunil V L 2023-12-18 20:32:39 +05:30 committed by Alistair Francis
parent 68c8b403c7
commit 0efb12b713
1 changed files with 39 additions and 4 deletions
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43
hw/riscv/virt-acpi-build.c
View file

@ -38,6 +38,7 @@
#include "hw/intc/riscv_aclint.h"
#define ACPI_BUILD_TABLE_SIZE 0x20000
#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
typedef struct AcpiBuildState {
/* Copy of table in RAM (for patching) */
@ -59,17 +60,50 @@ static void acpi_align_size(GArray *blob, unsigned align)
static void riscv_acpi_madt_add_rintc(uint32_t uid,
const CPUArchIdList *arch_ids,
GArray *entry)
GArray *entry,
RISCVVirtState *s)
{
uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
uint64_t hart_id = arch_ids->cpus[uid].arch_id;
uint32_t imsic_size, local_cpu_id, socket_id;
uint64_t imsic_socket_addr, imsic_addr;
MachineState *ms = MACHINE(s);
socket_id = arch_ids->cpus[uid].props.node_id;
local_cpu_id = (arch_ids->cpus[uid].arch_id -
riscv_socket_first_hartid(ms, socket_id)) %
riscv_socket_hart_count(ms, socket_id);
imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base +
(socket_id * VIRT_IMSIC_GROUP_MAX_SIZE);
imsic_size = IMSIC_HART_SIZE(guest_index_bits);
imsic_addr = imsic_socket_addr + local_cpu_id * imsic_size;
build_append_int_noprefix(entry, 0x18, 1); /* Type */
build_append_int_noprefix(entry, 20, 1); /* Length */
build_append_int_noprefix(entry, 36, 1); /* Length */
build_append_int_noprefix(entry, 1, 1); /* Version */
build_append_int_noprefix(entry, 0, 1); /* Reserved */
build_append_int_noprefix(entry, 0x1, 4); /* Flags */
build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */
build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */
/* External Interrupt Controller ID */
if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
build_append_int_noprefix(entry,
ACPI_BUILD_INTC_ID(
arch_ids->cpus[uid].props.node_id,
local_cpu_id),
4);
} else {
build_append_int_noprefix(entry, 0, 4);
}
if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
/* IMSIC Base address */
build_append_int_noprefix(entry, imsic_addr, 8);
/* IMSIC Size */
build_append_int_noprefix(entry, imsic_size, 4);
} else {
build_append_int_noprefix(entry, 0, 8);
build_append_int_noprefix(entry, 0, 4);
}
}
static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
@ -88,7 +122,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
aml_int(arch_ids->cpus[i].arch_id)));
/* build _MAT object */
riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf);
riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf, s);
aml_append(dev, aml_name_decl("_MAT",
aml_buffer(madt_buf->len,
(uint8_t *)madt_buf->data)));
@ -227,6 +261,7 @@ static void build_dsdt(GArray *table_data,
* 5.2.12 Multiple APIC Description Table (MADT)
* REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15
* https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
* https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view
*/
static void build_madt(GArray *table_data,
BIOSLinker *linker,
@ -246,7 +281,7 @@ static void build_madt(GArray *table_data,
/* RISC-V Local INTC structures per HART */
for (int i = 0; i < arch_ids->len; i++) {
riscv_acpi_madt_add_rintc(i, arch_ids, table_data);
riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s);
}
acpi_table_end(linker, &table);