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ia64 support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@115 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
fe1e3ce3e9
commit
0d3301964d
5 changed files with 154 additions and 1 deletions
108
elf.h
108
elf.h
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@ -767,6 +767,114 @@ typedef struct {
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#define PF_HP_LAZYSWAP 0x04000000
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#define PF_HP_SBP 0x08000000
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/* IA-64 specific declarations. */
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/* Processor specific flags for the Ehdr e_flags field. */
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#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */
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#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */
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#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */
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/* Processor specific values for the Phdr p_type field. */
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#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */
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#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */
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/* Processor specific flags for the Phdr p_flags field. */
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#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */
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/* Processor specific values for the Shdr sh_type field. */
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#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */
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#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */
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/* Processor specific flags for the Shdr sh_flags field. */
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#define SHF_IA_64_SHORT 0x10000000 /* section near gp */
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#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */
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/* Processor specific values for the Dyn d_tag field. */
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#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0)
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#define DT_IA_64_NUM 1
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/* IA-64 relocations. */
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#define R_IA64_NONE 0x00 /* none */
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#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */
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#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */
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#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */
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#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */
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#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */
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#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */
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#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */
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#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */
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#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */
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#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */
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#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */
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#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */
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#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */
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#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */
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#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */
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#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */
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#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */
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#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */
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#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */
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#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */
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#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */
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#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */
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#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */
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#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */
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#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */
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#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */
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#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */
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#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */
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#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */
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#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */
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#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */
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#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */
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#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */
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#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */
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#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */
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#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */
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#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */
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#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */
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#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */
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#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */
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#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */
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#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */
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#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */
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#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */
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#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */
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#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */
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#define R_IA64_REL32MSB 0x6c /* data 4 + REL */
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#define R_IA64_REL32LSB 0x6d /* data 4 + REL */
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#define R_IA64_REL64MSB 0x6e /* data 8 + REL */
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#define R_IA64_REL64LSB 0x6f /* data 8 + REL */
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#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */
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#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */
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#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */
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#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */
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#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */
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#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */
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#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */
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#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */
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#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */
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#define R_IA64_COPY 0x84 /* copy relocation */
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#define R_IA64_SUB 0x85 /* Addend and symbol difference */
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#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */
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#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */
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#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */
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#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */
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#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */
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#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */
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#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */
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#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */
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#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */
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#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */
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#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */
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#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */
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#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */
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#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */
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#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */
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#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */
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#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */
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#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */
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#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */
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typedef struct elf32_rel {
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Elf32_Addr r_offset;
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@ -106,6 +106,12 @@ register unsigned int T1 asm("$10");
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register unsigned int A0 asm("$11");
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register struct CPUX86State *env asm("$12");
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#endif
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#ifdef __ia64__
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register unsigned int T0 asm("r24");
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register unsigned int T1 asm("r25");
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register unsigned int A0 asm("r26");
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register struct CPUX86State *env asm("r27");
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#endif
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/* force GCC to generate only one epilog at the end of the function */
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#define FORCE_RET() asm volatile ("");
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32
ia64-syscall.S
Normal file
32
ia64-syscall.S
Normal file
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@ -0,0 +1,32 @@
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/* derived from glibc sysdeps/unix/sysv/linux/ia64/sysdep.S */
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#define __ASSEMBLY__
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#include <asm/asmmacro.h>
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#include <asm/unistd.h>
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ENTRY(__syscall_error)
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.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(0)
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alloc r33=ar.pfs, 0, 4, 0, 0
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mov r32=rp
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.body
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mov r35=r8
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mov r34=r1
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;;
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br.call.sptk.many b0 = __errno_location
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.Lret0: /* force new bundle */
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st4 [r8]=r35
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mov r1=r34
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mov rp=r32
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mov r8=-1
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mov ar.pfs=r33
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br.ret.sptk.few b0
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END(__syscall_error)
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GLOBAL_ENTRY(__ia64_syscall)
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mov r15=r37 /* syscall number */
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break __BREAK_SYSCALL
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cmp.eq p6,p0=-1,r10 /* r10 = -1 on error */
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(p6) br.cond.spnt.few __syscall_error
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br.ret.sptk.few b0
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.endp __ia64_syscall
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@ -26,6 +26,13 @@
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#include <errno.h>
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#include <sys/ucontext.h>
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#ifdef __ia64__
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#undef uc_mcontext
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#undef uc_sigmask
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#undef uc_stack
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#undef uc_link
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#endif
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#include "qemu.h"
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//#define DEBUG_SIGNAL
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2
thunk.h
2
thunk.h
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@ -70,7 +70,7 @@
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#define TARGET_LONG_BITS 32
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#if defined(__alpha__)
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#if defined(__alpha__) || defined (__ia64__)
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#define HOST_LONG_BITS 64
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#else
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#define HOST_LONG_BITS 32
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