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target/sparc: Implement FPADDS, FPSUBS

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-11-04 20:54:48 -07:00
parent bc3f14a9ed
commit 0d1d3aaf64
2 changed files with 91 additions and 0 deletions
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9
target/sparc/insns.decode
View file

@ -448,6 +448,15 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r
FPSUB64 10 ..... 110110 ..... 0 0100 0110 ..... @d_d_d
FPADDS16 10 ..... 110110 ..... 0 0101 1000 ..... @d_d_d
FPADDS16s 10 ..... 110110 ..... 0 0101 1001 ..... @r_r_r
FPADDS32 10 ..... 110110 ..... 0 0101 1010 ..... @d_d_d
FPADDS32s 10 ..... 110110 ..... 0 0101 1011 ..... @r_r_r
FPSUBS16 10 ..... 110110 ..... 0 0101 1100 ..... @d_d_d
FPSUBS16s 10 ..... 110110 ..... 0 0101 1101 ..... @r_r_r
FPSUBS32 10 ..... 110110 ..... 0 0101 1110 ..... @d_d_d
FPSUBS32s 10 ..... 110110 ..... 0 0101 1111 ..... @r_r_r
FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @d_d_d
FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r
FANDNOTd 10 ..... 110110 ..... 0 0110 0100 ..... @d_d_d # FANDNOT2d

82
target/sparc/translate.c
View file

@ -698,6 +698,78 @@ static void gen_op_fpack32(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2)
#endif
}
static void gen_op_fpadds16s(TCGv_i32 d, TCGv_i32 src1, TCGv_i32 src2)
{
TCGv_i32 t[2];
for (int i = 0; i < 2; i++) {
TCGv_i32 u = tcg_temp_new_i32();
TCGv_i32 v = tcg_temp_new_i32();
tcg_gen_sextract_i32(u, src1, i * 16, 16);
tcg_gen_sextract_i32(v, src2, i * 16, 16);
tcg_gen_add_i32(u, u, v);
tcg_gen_smax_i32(u, u, tcg_constant_i32(INT16_MIN));
tcg_gen_smin_i32(u, u, tcg_constant_i32(INT16_MAX));
t[i] = u;
}
tcg_gen_deposit_i32(d, t[0], t[1], 16, 16);
}
static void gen_op_fpsubs16s(TCGv_i32 d, TCGv_i32 src1, TCGv_i32 src2)
{
TCGv_i32 t[2];
for (int i = 0; i < 2; i++) {
TCGv_i32 u = tcg_temp_new_i32();
TCGv_i32 v = tcg_temp_new_i32();
tcg_gen_sextract_i32(u, src1, i * 16, 16);
tcg_gen_sextract_i32(v, src2, i * 16, 16);
tcg_gen_sub_i32(u, u, v);
tcg_gen_smax_i32(u, u, tcg_constant_i32(INT16_MIN));
tcg_gen_smin_i32(u, u, tcg_constant_i32(INT16_MAX));
t[i] = u;
}
tcg_gen_deposit_i32(d, t[0], t[1], 16, 16);
}
static void gen_op_fpadds32s(TCGv_i32 d, TCGv_i32 src1, TCGv_i32 src2)
{
TCGv_i32 r = tcg_temp_new_i32();
TCGv_i32 t = tcg_temp_new_i32();
TCGv_i32 v = tcg_temp_new_i32();
TCGv_i32 z = tcg_constant_i32(0);
tcg_gen_add_i32(r, src1, src2);
tcg_gen_xor_i32(t, src1, src2);
tcg_gen_xor_i32(v, r, src2);
tcg_gen_andc_i32(v, v, t);
tcg_gen_setcond_i32(TCG_COND_GE, t, r, z);
tcg_gen_addi_i32(t, t, INT32_MAX);
tcg_gen_movcond_i32(TCG_COND_LT, d, v, z, t, r);
}
static void gen_op_fpsubs32s(TCGv_i32 d, TCGv_i32 src1, TCGv_i32 src2)
{
TCGv_i32 r = tcg_temp_new_i32();
TCGv_i32 t = tcg_temp_new_i32();
TCGv_i32 v = tcg_temp_new_i32();
TCGv_i32 z = tcg_constant_i32(0);
tcg_gen_sub_i32(r, src1, src2);
tcg_gen_xor_i32(t, src1, src2);
tcg_gen_xor_i32(v, r, src1);
tcg_gen_and_i32(v, v, t);
tcg_gen_setcond_i32(TCG_COND_GE, t, r, z);
tcg_gen_addi_i32(t, t, INT32_MAX);
tcg_gen_movcond_i32(TCG_COND_LT, d, v, z, t, r);
}
static void gen_op_faligndata(TCGv_i64 dst, TCGv_i64 s1, TCGv_i64 s2)
{
#ifdef TARGET_SPARC64
@ -4788,6 +4860,11 @@ TRANS(FHADDs, VIS3, do_fff, a, gen_op_fhadds)
TRANS(FHSUBs, VIS3, do_fff, a, gen_op_fhsubs)
TRANS(FNHADDs, VIS3, do_fff, a, gen_op_fnhadds)
TRANS(FPADDS16s, VIS3, do_fff, a, gen_op_fpadds16s)
TRANS(FPSUBS16s, VIS3, do_fff, a, gen_op_fpsubs16s)
TRANS(FPADDS32s, VIS3, do_fff, a, gen_op_fpadds32s)
TRANS(FPSUBS32s, VIS3, do_fff, a, gen_op_fpsubs32s)
static bool do_env_fff(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32))
{
@ -4875,6 +4952,11 @@ TRANS(FPSUB32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sub)
TRANS(FCHKSM16, VIS3, do_gvec_ddd, a, MO_16, gen_op_fchksm16)
TRANS(FMEAN16, VIS3, do_gvec_ddd, a, MO_16, gen_op_fmean16)
TRANS(FPADDS16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_ssadd)
TRANS(FPADDS32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_ssadd)
TRANS(FPSUBS16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sssub)
TRANS(FPSUBS32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sssub)
static bool do_ddd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i64, TCGv_i64, TCGv_i64))
{