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hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4

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Speeds up PIIX4 which resolves an old TODO. Also makes PIIX4 compatible with Xen
which relies on pci_bus_fire_intx_routing_notifier() to be fired.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-27-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Bernhard Beschow 2023-10-07 14:38:34 +02:00 committed by Michael S. Tsirkin
parent 2a62c47926
commit 0c9fd5a309
1 changed files with 3 additions and 24 deletions
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27
hw/isa/piix.c
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@ -81,27 +81,6 @@ static void piix_set_pci_irq(void *opaque, int pirq, int level)
piix_set_pci_irq_level(s, pirq, level); piix_set_pci_irq_level(s, pirq, level);
} }
static void piix4_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
PIIXState *s = opaque;
PCIBus *bus = pci_get_bus(&s->dev);
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
if (pic_irq < ISA_NUM_IRQS) {
/* The pic level is the logical OR of all the PCI irqs mapped to it. */
pic_level = 0;
for (i = 0; i < PIIX_NUM_PIRQS; i++) {
if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
pic_level |= pci_bus_get_irq_level(bus, i);
}
}
qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level);
}
}
static void piix_request_i8259_irq(void *opaque, int irq, int level) static void piix_request_i8259_irq(void *opaque, int irq, int level)
{ {
PIIXState *s = opaque; PIIXState *s = opaque;
@ -223,7 +202,7 @@ static int piix4_post_load(void *opaque, int version_id)
s->rcr = 0; s->rcr = 0;
} }
return 0; return piix_post_load(opaque, version_id);
} }
static int piix3_pre_save(void *opaque) static int piix3_pre_save(void *opaque)
@ -442,6 +421,7 @@ static void pci_piix_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
k->config_write = piix_write_config;
dc->reset = piix_reset; dc->reset = piix_reset;
dc->desc = "ISA bridge"; dc->desc = "ISA bridge";
dc->hotpluggable = false; dc->hotpluggable = false;
@ -497,7 +477,6 @@ static void piix3_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->config_write = piix_write_config;
k->realize = piix3_realize; k->realize = piix3_realize;
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
@ -522,7 +501,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
return; return;
} }
pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); pci_bus_irqs(pci_bus, piix_set_pci_irq, s, PIIX_NUM_PIRQS);
} }
static void piix4_init(Object *obj) static void piix4_init(Object *obj)