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target/i386: convert CMPXCHG to new decoder
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
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@ -1165,6 +1165,8 @@ static const X86OpEntry opcodes_0F[256] = {
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[0xa4] = X86_OP_ENTRY4(SHLD, E,v, 2op,v, G,v),
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[0xa4] = X86_OP_ENTRY4(SHLD, E,v, 2op,v, G,v),
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[0xa5] = X86_OP_ENTRY3(SHLD, E,v, 2op,v, G,v),
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[0xa5] = X86_OP_ENTRY3(SHLD, E,v, 2op,v, G,v),
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[0xb0] = X86_OP_ENTRY2(CMPXCHG,E,b, G,b, lock),
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[0xb1] = X86_OP_ENTRY2(CMPXCHG,E,v, G,v, lock),
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[0xb2] = X86_OP_ENTRY3(LSS, G,v, EM,p, None, None),
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[0xb2] = X86_OP_ENTRY3(LSS, G,v, EM,p, None, None),
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[0xb4] = X86_OP_ENTRY3(LFS, G,v, EM,p, None, None),
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[0xb4] = X86_OP_ENTRY3(LFS, G,v, EM,p, None, None),
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[0xb5] = X86_OP_ENTRY3(LGS, G,v, EM,p, None, None),
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[0xb5] = X86_OP_ENTRY3(LGS, G,v, EM,p, None, None),
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@ -2597,7 +2599,6 @@ static void disas_insn(DisasContext *s, CPUState *cpu)
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case 0x1a ... 0x1b: /* MPX */
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case 0x1a ... 0x1b: /* MPX */
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case 0xa3: /* bt */
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case 0xa3: /* bt */
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case 0xab: /* bts */
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case 0xab: /* bts */
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case 0xb0 ... 0xb1: /* cmpxchg */
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case 0xb3: /* btr */
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case 0xb3: /* btr */
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case 0xba ... 0xbb: /* grp8, btc */
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case 0xba ... 0xbb: /* grp8, btc */
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case 0xc7: /* grp9 */
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case 0xc7: /* grp9 */
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@ -1586,6 +1586,57 @@ static void gen_CMPS(DisasContext *s, X86DecodedInsn *decode)
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}
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}
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}
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}
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static void gen_CMPXCHG(DisasContext *s, X86DecodedInsn *decode)
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{
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MemOp ot = decode->op[2].ot;
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TCGv cmpv = tcg_temp_new();
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TCGv oldv = tcg_temp_new();
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TCGv newv = tcg_temp_new();
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TCGv dest;
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tcg_gen_ext_tl(cmpv, cpu_regs[R_EAX], ot);
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tcg_gen_ext_tl(newv, s->T1, ot);
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if (s->prefix & PREFIX_LOCK) {
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tcg_gen_atomic_cmpxchg_tl(oldv, s->A0, cmpv, newv,
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s->mem_index, ot | MO_LE);
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} else {
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tcg_gen_ext_tl(oldv, s->T0, ot);
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if (decode->op[0].has_ea) {
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/*
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* Perform an unconditional store cycle like physical cpu;
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* must be before changing accumulator to ensure
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* idempotency if the store faults and the instruction
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* is restarted
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*/
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tcg_gen_movcond_tl(TCG_COND_EQ, newv, oldv, cmpv, newv, oldv);
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gen_op_st_v(s, ot, newv, s->A0);
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} else {
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/*
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* Unlike the memory case, where "the destination operand receives
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* a write cycle without regard to the result of the comparison",
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* rm must not be touched altogether if the write fails, including
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* not zero-extending it on 64-bit processors. So, precompute
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* the result of a successful writeback and perform the movcond
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* directly on cpu_regs. In case rm is part of RAX, note that this
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* movcond and the one below are mutually exclusive is executed.
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*/
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dest = gen_op_deposit_reg_v(s, ot, decode->op[0].n, newv, newv);
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tcg_gen_movcond_tl(TCG_COND_EQ, dest, oldv, cmpv, newv, dest);
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}
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decode->op[0].unit = X86_OP_SKIP;
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}
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/* Write RAX only if the cmpxchg fails. */
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dest = gen_op_deposit_reg_v(s, ot, R_EAX, s->T0, oldv);
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tcg_gen_movcond_tl(TCG_COND_NE, dest, oldv, cmpv, s->T0, dest);
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tcg_gen_mov_tl(s->cc_srcT, cmpv);
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tcg_gen_sub_tl(cmpv, cmpv, oldv);
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decode->cc_dst = cmpv;
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decode->cc_src = oldv;
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decode->cc_op = CC_OP_SUBB + ot;
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}
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static void gen_CPUID(DisasContext *s, X86DecodedInsn *decode)
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static void gen_CPUID(DisasContext *s, X86DecodedInsn *decode)
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{
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{
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gen_update_cc_op(s);
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gen_update_cc_op(s);
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@ -434,13 +434,6 @@ static inline MemOp mo_stacksize(DisasContext *s)
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return CODE64(s) ? MO_64 : SS32(s) ? MO_32 : MO_16;
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return CODE64(s) ? MO_64 : SS32(s) ? MO_32 : MO_16;
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}
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}
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/* Select size 8 if lsb of B is clear, else OT. Used for decoding
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byte vs word opcodes. */
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static inline MemOp mo_b_d(int b, MemOp ot)
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{
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return b & 1 ? ot : MO_8;
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}
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/* Compute the result of writing t0 to the OT-sized register REG.
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/* Compute the result of writing t0 to the OT-sized register REG.
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*
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*
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* If DEST is NULL, store the result into the register and return the
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* If DEST is NULL, store the result into the register and return the
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@ -715,11 +708,6 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, MemOp size, bool sign)
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return dst;
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return dst;
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}
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}
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static void gen_extu(MemOp ot, TCGv reg)
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{
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gen_ext_tl(reg, reg, ot, false);
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}
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static void gen_exts(MemOp ot, TCGv reg)
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static void gen_exts(MemOp ot, TCGv reg)
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{
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{
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gen_ext_tl(reg, reg, ot, true);
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gen_ext_tl(reg, reg, ot, true);
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@ -3003,73 +2991,6 @@ static void disas_insn_old(DisasContext *s, CPUState *cpu, int b)
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/* now check op code */
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/* now check op code */
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switch (b) {
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switch (b) {
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/**************************/
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/* arith & logic */
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case 0x1b0:
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case 0x1b1: /* cmpxchg Ev, Gv */
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{
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TCGv oldv, newv, cmpv, dest;
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ot = mo_b_d(b, dflag);
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modrm = x86_ldub_code(env, s);
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reg = ((modrm >> 3) & 7) | REX_R(s);
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mod = (modrm >> 6) & 3;
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oldv = tcg_temp_new();
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newv = tcg_temp_new();
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cmpv = tcg_temp_new();
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gen_op_mov_v_reg(s, ot, newv, reg);
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tcg_gen_mov_tl(cmpv, cpu_regs[R_EAX]);
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gen_extu(ot, cmpv);
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if (s->prefix & PREFIX_LOCK) {
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if (mod == 3) {
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goto illegal_op;
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}
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gen_lea_modrm(env, s, modrm);
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tcg_gen_atomic_cmpxchg_tl(oldv, s->A0, cmpv, newv,
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s->mem_index, ot | MO_LE);
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} else {
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if (mod == 3) {
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rm = (modrm & 7) | REX_B(s);
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gen_op_mov_v_reg(s, ot, oldv, rm);
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gen_extu(ot, oldv);
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/*
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* Unlike the memory case, where "the destination operand receives
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* a write cycle without regard to the result of the comparison",
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* rm must not be touched altogether if the write fails, including
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* not zero-extending it on 64-bit processors. So, precompute
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* the result of a successful writeback and perform the movcond
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* directly on cpu_regs. Also need to write accumulator first, in
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* case rm is part of RAX too.
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*/
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dest = gen_op_deposit_reg_v(s, ot, rm, newv, newv);
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tcg_gen_movcond_tl(TCG_COND_EQ, dest, oldv, cmpv, newv, dest);
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} else {
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gen_lea_modrm(env, s, modrm);
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gen_op_ld_v(s, ot, oldv, s->A0);
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/*
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* Perform an unconditional store cycle like physical cpu;
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* must be before changing accumulator to ensure
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* idempotency if the store faults and the instruction
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* is restarted
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*/
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tcg_gen_movcond_tl(TCG_COND_EQ, newv, oldv, cmpv, newv, oldv);
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gen_op_st_v(s, ot, newv, s->A0);
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}
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}
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/*
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* Write EAX only if the cmpxchg fails; reuse newv as the destination,
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* since it's dead here.
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*/
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dest = gen_op_deposit_reg_v(s, ot, R_EAX, newv, oldv);
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tcg_gen_movcond_tl(TCG_COND_EQ, dest, oldv, cmpv, dest, newv);
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tcg_gen_mov_tl(cpu_cc_src, oldv);
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tcg_gen_mov_tl(s->cc_srcT, cmpv);
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tcg_gen_sub_tl(cpu_cc_dst, cmpv, oldv);
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set_cc_op(s, CC_OP_SUBB + ot);
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}
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break;
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case 0x1c7: /* cmpxchg8b */
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case 0x1c7: /* cmpxchg8b */
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modrm = x86_ldub_code(env, s);
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modrm = x86_ldub_code(env, s);
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mod = (modrm >> 6) & 3;
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mod = (modrm >> 6) & 3;
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