system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-10-07 03:29:37 +00:00
Code Issues Packages Projects Releases Wiki Activity

tcg/tci: Use helper_{ld,st}*_mmu for user-only

Browse source 
We can now fold these two pieces of code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-03-08 15:43:41 -08:00
parent de95016dfb
commit 0bbf501570
1 changed files with 0 additions and 89 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

89
tcg/tci.c
View file

@ -292,7 +292,6 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
MemOp mop = get_memop(oi);
uintptr_t ra = (uintptr_t)tb_ptr;
#ifdef CONFIG_SOFTMMU
switch (mop & MO_SSIZE) {
case MO_UB:
return helper_ldub_mmu(env, taddr, oi, ra);
@ -311,58 +310,6 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
default:
g_assert_not_reached();
}
#else
void *haddr = g2h(env_cpu(env), taddr);
unsigned a_mask = (1u << get_alignment_bits(mop)) - 1;
uint64_t ret;
set_helper_retaddr(ra);
if (taddr & a_mask) {
helper_unaligned_ld(env, taddr);
}
switch (mop & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
ret = ldub_p(haddr);
break;
case MO_SB:
ret = ldsb_p(haddr);
break;
case MO_LEUW:
ret = lduw_le_p(haddr);
break;
case MO_LESW:
ret = ldsw_le_p(haddr);
break;
case MO_LEUL:
ret = (uint32_t)ldl_le_p(haddr);
break;
case MO_LESL:
ret = (int32_t)ldl_le_p(haddr);
break;
case MO_LEUQ:
ret = ldq_le_p(haddr);
break;
case MO_BEUW:
ret = lduw_be_p(haddr);
break;
case MO_BESW:
ret = ldsw_be_p(haddr);
break;
case MO_BEUL:
ret = (uint32_t)ldl_be_p(haddr);
break;
case MO_BESL:
ret = (int32_t)ldl_be_p(haddr);
break;
case MO_BEUQ:
ret = ldq_be_p(haddr);
break;
default:
g_assert_not_reached();
}
clear_helper_retaddr();
return ret;
#endif
}
static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
@ -371,7 +318,6 @@ static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
MemOp mop = get_memop(oi);
uintptr_t ra = (uintptr_t)tb_ptr;
#ifdef CONFIG_SOFTMMU
switch (mop & MO_SIZE) {
case MO_UB:
helper_stb_mmu(env, taddr, val, oi, ra);
@ -388,41 +334,6 @@ static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
default:
g_assert_not_reached();
}
#else
void *haddr = g2h(env_cpu(env), taddr);
unsigned a_mask = (1u << get_alignment_bits(mop)) - 1;
set_helper_retaddr(ra);
if (taddr & a_mask) {
helper_unaligned_st(env, taddr);
}
switch (mop & (MO_BSWAP | MO_SIZE)) {
case MO_UB:
stb_p(haddr, val);
break;
case MO_LEUW:
stw_le_p(haddr, val);
break;
case MO_LEUL:
stl_le_p(haddr, val);
break;
case MO_LEUQ:
stq_le_p(haddr, val);
break;
case MO_BEUW:
stw_be_p(haddr, val);
break;
case MO_BEUL:
stl_be_p(haddr, val);
break;
case MO_BEUQ:
stq_be_p(haddr, val);
break;
default:
g_assert_not_reached();
}
clear_helper_retaddr();
#endif
}
#if TCG_TARGET_REG_BITS == 64