Hexagon (target/hexagon) add A6_vminub_RdP

Rdd32,Pe4 = vminub(Rtt32, Rss32)
    Vector min of bytes

Test cases in tests/tcg/hexagon/multi_result.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-21-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Taylor Simpson 2021-04-08 20:07:48 -05:00 committed by Richard Henderson
parent da74cd2dce
commit 0a65d28693
5 changed files with 94 additions and 0 deletions

View file

@ -237,6 +237,33 @@
tcg_temp_free_i64(tmp); \
} while (0)
/*
* Compare each of the 8 unsigned bytes
* The minimum is placed in each byte of the destination.
* Each bit of the predicate is set true if the bit from the first operand
* is greater than the bit from the second operand.
* r5:4,p1 = vminub(r1:0, r3:2)
*/
#define fGEN_TCG_A6_vminub_RdP(SHORTCODE) \
do { \
TCGv left = tcg_temp_new(); \
TCGv right = tcg_temp_new(); \
TCGv tmp = tcg_temp_new(); \
tcg_gen_movi_tl(PeV, 0); \
tcg_gen_movi_i64(RddV, 0); \
for (int i = 0; i < 8; i++) { \
gen_get_byte_i64(left, i, RttV, false); \
gen_get_byte_i64(right, i, RssV, false); \
tcg_gen_setcond_tl(TCG_COND_GT, tmp, left, right); \
tcg_gen_deposit_tl(PeV, PeV, tmp, i, 1); \
tcg_gen_umin_tl(tmp, left, right); \
gen_set_byte_i64(i, RddV, tmp); \
} \
tcg_temp_free(left); \
tcg_temp_free(right); \
tcg_temp_free(tmp); \
} while (0)
/* Floating point */
#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
gen_helper_conv_sf2df(RddV, cpu_env, RsV)

View file

@ -266,6 +266,28 @@ static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
}
}
static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
{
TCGv_i64 res64 = tcg_temp_new_i64();
if (sign) {
tcg_gen_sextract_i64(res64, src, N * 8, 8);
} else {
tcg_gen_extract_i64(res64, src, N * 8, 8);
}
tcg_gen_extrl_i64_i32(result, res64);
tcg_temp_free_i64(res64);
return result;
}
static void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
{
TCGv_i64 src64 = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(src64, src);
tcg_gen_deposit_i64(result, result, src64, N * 8, 8);
tcg_temp_free_i64(src64);
}
static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
{
tcg_gen_qemu_ld32u(dest, vaddr, mem_index);

View file

@ -1259,6 +1259,16 @@ Q6INSN(A5_ACS,"Rxx32,Pe4=vacsh(Rss32,Rtt32)",ATTRIBS(),
}
})
Q6INSN(A6_vminub_RdP,"Rdd32,Pe4=vminub(Rtt32,Rss32)",ATTRIBS(),
"Vector minimum of bytes, records minimum and decision vector",
{
fHIDE(int i;)
for (i = 0; i < 8; i++) {
fSETBIT(i, PeV, (fGETUBYTE(i,RttV) > fGETUBYTE(i,RssV)));
fSETBYTE(i,RddV,fMIN(fGETUBYTE(i,RttV),fGETUBYTE(i,RssV)));
}
})
/**********************************************/
/* Vector Min/Max */
/**********************************************/

View file

@ -1018,6 +1018,7 @@ MPY_ENC(M7_dcmpyiwc_acc, "1010","xxxxx","1","0","1","0","10")
MPY_ENC(A5_ACS, "1010","xxxxx","0","1","0","1","ee")
MPY_ENC(A6_vminub_RdP, "1010","ddddd","0","1","1","1","ee")
/*
*/

View file

@ -70,6 +70,21 @@ static long long vacsh(long long Rxx, long long Rss, long long Rtt,
return result;
}
static long long vminub(long long Rtt, long long Rss,
int *pred_result)
{
long long result;
int predval;
asm volatile("%0,p0 = vminub(%2, %3)\n\t"
"%1 = p0\n\t"
: "=r"(result), "=r"(predval)
: "r"(Rtt), "r"(Rss)
: "p0");
*pred_result = predval;
return result;
}
int err;
static void check_ll(long long val, long long expect)
@ -155,11 +170,30 @@ static void test_vacsh()
check(ovf_result, 0);
}
static void test_vminub()
{
long long res64;
int pred_result;
res64 = vminub(0x0807060504030201LL,
0x0102030405060708LL,
&pred_result);
check_ll(res64, 0x0102030404030201LL);
check_p(pred_result, 0xf0);
res64 = vminub(0x0802060405030701LL,
0x0107030504060208LL,
&pred_result);
check_ll(res64, 0x0102030404030201LL);
check_p(pred_result, 0xaa);
}
int main()
{
test_sfrecipa();
test_sfinvsqrta();
test_vacsh();
test_vminub();
puts(err ? "FAIL" : "PASS");
return err;