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target/mips: Extract trap code into env->error_code
Simplify cpu_loop by doing all of the decode in translate. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-18-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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@ -197,51 +197,12 @@ done_syscall:
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do_tr_or_bp(env, code, false);
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break;
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case EXCP_TRAP:
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{
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abi_ulong trap_instr;
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unsigned int code = 0;
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/*
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* FIXME: It would be better to decode the trap number
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* during translate, and store it in error_code while
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* raising the exception. We should not be re-reading
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* the opcode here.
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*/
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if (env->hflags & MIPS_HFLAG_M16) {
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/* microMIPS mode */
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abi_ulong instr[2];
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ret = get_user_u16(instr[0], env->active_tc.PC) ||
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get_user_u16(instr[1], env->active_tc.PC + 2);
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trap_instr = (instr[0] << 16) | instr[1];
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} else {
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ret = get_user_u32(trap_instr, env->active_tc.PC);
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}
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if (ret != 0) {
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goto error;
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}
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/* The immediate versions don't provide a code. */
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if (!(trap_instr & 0xFC000000)) {
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if (env->hflags & MIPS_HFLAG_M16) {
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/* microMIPS mode */
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code = ((trap_instr >> 12) & ((1 << 4) - 1));
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} else {
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code = ((trap_instr >> 6) & ((1 << 10) - 1));
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}
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}
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do_tr_or_bp(env, code, true);
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}
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do_tr_or_bp(env, env->error_code, true);
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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error:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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abort();
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}
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@ -1047,7 +1047,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
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case TNE:
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mips32_op = OPC_TNE;
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do_trap:
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gen_trap(ctx, mips32_op, rs, rt, -1);
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gen_trap(ctx, mips32_op, rs, rt, -1, extract32(ctx->opcode, 12, 4));
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break;
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#ifndef CONFIG_USER_ONLY
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case MFC0:
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@ -2439,7 +2439,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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check_insn_opc_removed(ctx, ISA_MIPS_R6);
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mips32_op = OPC_TEQI;
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do_trapi:
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gen_trap(ctx, mips32_op, rs, -1, imm);
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gen_trap(ctx, mips32_op, rs, -1, imm, 0);
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break;
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case BNEZC:
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@ -1268,11 +1268,11 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
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switch (extract32(ctx->opcode, 10, 1)) {
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case NM_TEQ:
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check_nms(ctx);
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gen_trap(ctx, OPC_TEQ, rs, rt, -1);
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gen_trap(ctx, OPC_TEQ, rs, rt, -1, rd);
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break;
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case NM_TNE:
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check_nms(ctx);
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gen_trap(ctx, OPC_TNE, rs, rt, -1);
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gen_trap(ctx, OPC_TNE, rs, rt, -1, rd);
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break;
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}
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break;
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@ -4733,7 +4733,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
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/* Traps */
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static void gen_trap(DisasContext *ctx, uint32_t opc,
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int rs, int rt, int16_t imm)
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int rs, int rt, int16_t imm, int code)
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{
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int cond;
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TCGv t0 = tcg_temp_new();
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@ -4778,6 +4778,11 @@ static void gen_trap(DisasContext *ctx, uint32_t opc,
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case OPC_TGEU: /* rs >= rs unsigned */
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case OPC_TGEIU: /* r0 >= 0 unsigned */
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/* Always trap */
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#ifdef CONFIG_USER_ONLY
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/* Pass the break code along to cpu_loop. */
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tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
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offsetof(CPUMIPSState, error_code));
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#endif
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generate_exception_end(ctx, EXCP_TRAP);
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break;
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case OPC_TLT: /* rs < rs */
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@ -4818,6 +4823,18 @@ static void gen_trap(DisasContext *ctx, uint32_t opc,
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tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1);
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break;
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}
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#ifdef CONFIG_USER_ONLY
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/* Pass the break code along to cpu_loop. */
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tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
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offsetof(CPUMIPSState, error_code));
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#endif
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/* Like save_cpu_state, only don't update saved values. */
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if (ctx->base.pc_next != ctx->saved_pc) {
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gen_save_pc(ctx->base.pc_next);
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}
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if (ctx->hflags != ctx->saved_hflags) {
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tcg_gen_movi_i32(hflags, ctx->hflags);
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}
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generate_exception(ctx, EXCP_TRAP);
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gen_set_label(l1);
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}
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@ -14155,7 +14172,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
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case OPC_TEQ:
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case OPC_TNE:
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check_insn(ctx, ISA_MIPS2);
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gen_trap(ctx, op1, rs, rt, -1);
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gen_trap(ctx, op1, rs, rt, -1, extract32(ctx->opcode, 6, 10));
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break;
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case OPC_PMON:
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/* Pmon entry point, also R4010 selsl */
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@ -15289,11 +15306,10 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
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case OPC_TLTI:
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case OPC_TLTIU:
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case OPC_TEQI:
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case OPC_TNEI:
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check_insn(ctx, ISA_MIPS2);
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check_insn_opc_removed(ctx, ISA_MIPS_R6);
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gen_trap(ctx, op1, rs, -1, imm);
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gen_trap(ctx, op1, rs, -1, imm, 0);
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break;
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case OPC_SIGRIE:
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check_insn(ctx, ISA_MIPS_R6);
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