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target/riscv: Remove the hret instruction

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The hret instruction does not exist in the new spec versions, so remove
it from QEMU.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Alistair Francis 2020-01-31 17:02:38 -08:00 committed by Palmer Dabbelt
parent 895c412cb6
commit 0736febb2d
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GPG key ID: 2E1319F35FBB1889
2 changed files with 0 additions and 6 deletions
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1
target/riscv/insn32.decode
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@ -75,7 +75,6 @@ ecall 000000000000 00000 000 00000 1110011
ebreak 000000000001 00000 000 00000 1110011
uret 0000000 00010 00000 000 00000 1110011
sret 0001000 00010 00000 000 00000 1110011
hret 0010000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011
wfi 0001000 00101 00000 000 00000 1110011
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma

5
target/riscv/insn_trans/trans_privileged.inc.c
View file

@ -58,11 +58,6 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
#endif
}
static bool trans_hret(DisasContext *ctx, arg_hret *a)
{
return false;
}
static bool trans_mret(DisasContext *ctx, arg_mret *a)
{
#ifndef CONFIG_USER_ONLY