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https://gitlab.com/qemu-project/qemu
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target-mips: replace cpu_save/cpu_load with VMStateDescription
Create VMStateDescription for MIPS CPU. The new structure contains exactly the same fields as before, therefore leaving existing version_id. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Leon Alrae
parent
4841237141
commit
04cd79625f
4 changed files with 276 additions and 336 deletions
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@ -74,6 +74,10 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
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#define ENV_OFFSET offsetof(MIPSCPU, env)
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#ifndef CONFIG_USER_ONLY
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extern const struct VMStateDescription vmstate_mips_cpu;
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#endif
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void mips_cpu_do_interrupt(CPUState *cpu);
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bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
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void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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@ -148,6 +148,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
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cc->do_unassigned_access = mips_cpu_unassigned_access;
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cc->do_unaligned_access = mips_cpu_do_unaligned_access;
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cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
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cc->vmsd = &vmstate_mips_cpu;
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#endif
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cc->gdb_num_core_regs = 73;
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@ -614,8 +614,6 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
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extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
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extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
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#define CPU_SAVE_VERSION 5
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/* MMU modes definitions. We carefully match the indices with our
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hflags layout. */
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#define MMU_MODE0_SUFFIX _kernel
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@ -1,341 +1,278 @@
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "cpu.h"
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static void save_tc(QEMUFile *f, TCState *tc)
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/* FPU state */
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static int get_fpr(QEMUFile *f, void *pv, size_t size)
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{
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int i;
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/* Save active TC */
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for(i = 0; i < 32; i++)
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qemu_put_betls(f, &tc->gpr[i]);
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qemu_put_betls(f, &tc->PC);
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for(i = 0; i < MIPS_DSP_ACC; i++)
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qemu_put_betls(f, &tc->HI[i]);
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for(i = 0; i < MIPS_DSP_ACC; i++)
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qemu_put_betls(f, &tc->LO[i]);
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for(i = 0; i < MIPS_DSP_ACC; i++)
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qemu_put_betls(f, &tc->ACX[i]);
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qemu_put_betls(f, &tc->DSPControl);
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qemu_put_sbe32s(f, &tc->CP0_TCStatus);
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qemu_put_sbe32s(f, &tc->CP0_TCBind);
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qemu_put_betls(f, &tc->CP0_TCHalt);
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qemu_put_betls(f, &tc->CP0_TCContext);
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qemu_put_betls(f, &tc->CP0_TCSchedule);
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qemu_put_betls(f, &tc->CP0_TCScheFBack);
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qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
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qemu_put_betls(f, &tc->CP0_UserLocal);
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}
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static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
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{
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int i;
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for(i = 0; i < 32; i++)
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qemu_put_be64s(f, &fpu->fpr[i].d);
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qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess);
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qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode);
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qemu_put_s8s(f, &fpu->fp_status.float_exception_flags);
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qemu_put_be32s(f, &fpu->fcr0);
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qemu_put_be32s(f, &fpu->fcr31);
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}
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void cpu_save(QEMUFile *f, void *opaque)
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{
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CPUMIPSState *env = opaque;
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int i;
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/* Save active TC */
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save_tc(f, &env->active_tc);
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/* Save active FPU */
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save_fpu(f, &env->active_fpu);
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/* Save MVP */
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qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
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qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
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qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
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/* Save TLB */
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qemu_put_be32s(f, &env->tlb->nb_tlb);
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qemu_put_be32s(f, &env->tlb->tlb_in_use);
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for(i = 0; i < MIPS_TLB_MAX; i++) {
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uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].EHINV << 15) |
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(env->tlb->mmu.r4k.tlb[i].RI1 << 14) |
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(env->tlb->mmu.r4k.tlb[i].RI0 << 13) |
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(env->tlb->mmu.r4k.tlb[i].XI1 << 12) |
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(env->tlb->mmu.r4k.tlb[i].XI0 << 11) |
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(env->tlb->mmu.r4k.tlb[i].G << 10) |
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(env->tlb->mmu.r4k.tlb[i].C0 << 7) |
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(env->tlb->mmu.r4k.tlb[i].C1 << 4) |
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(env->tlb->mmu.r4k.tlb[i].V0 << 3) |
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(env->tlb->mmu.r4k.tlb[i].V1 << 2) |
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(env->tlb->mmu.r4k.tlb[i].D0 << 1) |
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(env->tlb->mmu.r4k.tlb[i].D1 << 0));
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uint8_t asid;
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qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
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qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
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asid = env->tlb->mmu.r4k.tlb[i].ASID;
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qemu_put_8s(f, &asid);
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qemu_put_be16s(f, &flags);
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qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
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qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
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}
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/* Save CPU metastate */
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qemu_put_be32s(f, &env->current_tc);
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qemu_put_be32s(f, &env->current_fpu);
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qemu_put_sbe32s(f, &env->error_code);
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qemu_put_be32s(f, &env->hflags);
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qemu_put_betls(f, &env->btarget);
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i = env->bcond;
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qemu_put_sbe32s(f, &i);
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/* Save remaining CP1 registers */
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qemu_put_sbe32s(f, &env->CP0_Index);
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qemu_put_sbe32s(f, &env->CP0_Random);
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qemu_put_sbe32s(f, &env->CP0_VPEControl);
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qemu_put_sbe32s(f, &env->CP0_VPEConf0);
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qemu_put_sbe32s(f, &env->CP0_VPEConf1);
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qemu_put_betls(f, &env->CP0_YQMask);
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qemu_put_betls(f, &env->CP0_VPESchedule);
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qemu_put_betls(f, &env->CP0_VPEScheFBack);
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qemu_put_sbe32s(f, &env->CP0_VPEOpt);
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qemu_put_betls(f, &env->CP0_EntryLo0);
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qemu_put_betls(f, &env->CP0_EntryLo1);
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qemu_put_betls(f, &env->CP0_Context);
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qemu_put_sbe32s(f, &env->CP0_PageMask);
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qemu_put_sbe32s(f, &env->CP0_PageGrain);
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qemu_put_sbe32s(f, &env->CP0_Wired);
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qemu_put_sbe32s(f, &env->CP0_SRSConf0);
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qemu_put_sbe32s(f, &env->CP0_SRSConf1);
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qemu_put_sbe32s(f, &env->CP0_SRSConf2);
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qemu_put_sbe32s(f, &env->CP0_SRSConf3);
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qemu_put_sbe32s(f, &env->CP0_SRSConf4);
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qemu_put_sbe32s(f, &env->CP0_HWREna);
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qemu_put_betls(f, &env->CP0_BadVAddr);
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qemu_put_be32s(f, &env->CP0_BadInstr);
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qemu_put_be32s(f, &env->CP0_BadInstrP);
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qemu_put_sbe32s(f, &env->CP0_Count);
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qemu_put_betls(f, &env->CP0_EntryHi);
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qemu_put_sbe32s(f, &env->CP0_Compare);
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qemu_put_sbe32s(f, &env->CP0_Status);
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qemu_put_sbe32s(f, &env->CP0_IntCtl);
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qemu_put_sbe32s(f, &env->CP0_SRSCtl);
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qemu_put_sbe32s(f, &env->CP0_SRSMap);
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qemu_put_sbe32s(f, &env->CP0_Cause);
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qemu_put_betls(f, &env->CP0_EPC);
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qemu_put_sbe32s(f, &env->CP0_PRid);
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qemu_put_sbe32s(f, &env->CP0_EBase);
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qemu_put_sbe32s(f, &env->CP0_Config0);
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qemu_put_sbe32s(f, &env->CP0_Config1);
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qemu_put_sbe32s(f, &env->CP0_Config2);
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qemu_put_sbe32s(f, &env->CP0_Config3);
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qemu_put_sbe32s(f, &env->CP0_Config6);
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qemu_put_sbe32s(f, &env->CP0_Config7);
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qemu_put_betls(f, &env->lladdr);
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for(i = 0; i < 8; i++)
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qemu_put_betls(f, &env->CP0_WatchLo[i]);
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for(i = 0; i < 8; i++)
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qemu_put_sbe32s(f, &env->CP0_WatchHi[i]);
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qemu_put_betls(f, &env->CP0_XContext);
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qemu_put_sbe32s(f, &env->CP0_Framemask);
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qemu_put_sbe32s(f, &env->CP0_Debug);
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qemu_put_betls(f, &env->CP0_DEPC);
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qemu_put_sbe32s(f, &env->CP0_Performance0);
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qemu_put_sbe32s(f, &env->CP0_TagLo);
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qemu_put_sbe32s(f, &env->CP0_DataLo);
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qemu_put_sbe32s(f, &env->CP0_TagHi);
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qemu_put_sbe32s(f, &env->CP0_DataHi);
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qemu_put_betls(f, &env->CP0_ErrorEPC);
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qemu_put_sbe32s(f, &env->CP0_DESAVE);
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for (i = 0; i < MIPS_KSCRATCH_NUM; i++) {
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qemu_put_betls(f, &env->CP0_KScratch[i]);
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}
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/* Save inactive TC state */
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for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
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save_tc(f, &env->tcs[i]);
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for (i = 0; i < MIPS_FPU_MAX; i++)
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save_fpu(f, &env->fpus[i]);
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}
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static void load_tc(QEMUFile *f, TCState *tc, int version_id)
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{
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int i;
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/* Save active TC */
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for(i = 0; i < 32; i++)
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qemu_get_betls(f, &tc->gpr[i]);
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qemu_get_betls(f, &tc->PC);
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for(i = 0; i < MIPS_DSP_ACC; i++)
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qemu_get_betls(f, &tc->HI[i]);
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for(i = 0; i < MIPS_DSP_ACC; i++)
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qemu_get_betls(f, &tc->LO[i]);
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for(i = 0; i < MIPS_DSP_ACC; i++)
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qemu_get_betls(f, &tc->ACX[i]);
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qemu_get_betls(f, &tc->DSPControl);
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qemu_get_sbe32s(f, &tc->CP0_TCStatus);
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qemu_get_sbe32s(f, &tc->CP0_TCBind);
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qemu_get_betls(f, &tc->CP0_TCHalt);
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qemu_get_betls(f, &tc->CP0_TCContext);
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qemu_get_betls(f, &tc->CP0_TCSchedule);
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qemu_get_betls(f, &tc->CP0_TCScheFBack);
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qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
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if (version_id >= 4) {
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qemu_get_betls(f, &tc->CP0_UserLocal);
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}
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}
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static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
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{
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int i;
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for(i = 0; i < 32; i++)
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qemu_get_be64s(f, &fpu->fpr[i].d);
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qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess);
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qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode);
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qemu_get_s8s(f, &fpu->fp_status.float_exception_flags);
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qemu_get_be32s(f, &fpu->fcr0);
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qemu_get_be32s(f, &fpu->fcr31);
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}
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int cpu_load(QEMUFile *f, void *opaque, int version_id)
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{
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CPUMIPSState *env = opaque;
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MIPSCPU *cpu = mips_env_get_cpu(env);
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int i;
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if (version_id < 3) {
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return -EINVAL;
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}
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/* Load active TC */
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load_tc(f, &env->active_tc, version_id);
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/* Load active FPU */
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load_fpu(f, &env->active_fpu);
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/* Load MVP */
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qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl);
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qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0);
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qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);
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/* Load TLB */
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qemu_get_be32s(f, &env->tlb->nb_tlb);
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qemu_get_be32s(f, &env->tlb->tlb_in_use);
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for(i = 0; i < MIPS_TLB_MAX; i++) {
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uint16_t flags;
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uint8_t asid;
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qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
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qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
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qemu_get_8s(f, &asid);
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env->tlb->mmu.r4k.tlb[i].ASID = asid;
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qemu_get_be16s(f, &flags);
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env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1;
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env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
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env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
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env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
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env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
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env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
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env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
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if (version_id >= 5) {
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env->tlb->mmu.r4k.tlb[i].EHINV = (flags >> 15) & 1;
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env->tlb->mmu.r4k.tlb[i].RI1 = (flags >> 14) & 1;
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env->tlb->mmu.r4k.tlb[i].RI0 = (flags >> 13) & 1;
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env->tlb->mmu.r4k.tlb[i].XI1 = (flags >> 12) & 1;
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env->tlb->mmu.r4k.tlb[i].XI0 = (flags >> 11) & 1;
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}
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qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
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qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
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}
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/* Load CPU metastate */
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qemu_get_be32s(f, &env->current_tc);
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qemu_get_be32s(f, &env->current_fpu);
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qemu_get_sbe32s(f, &env->error_code);
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qemu_get_be32s(f, &env->hflags);
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qemu_get_betls(f, &env->btarget);
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qemu_get_sbe32s(f, &i);
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env->bcond = i;
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/* Load remaining CP1 registers */
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qemu_get_sbe32s(f, &env->CP0_Index);
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qemu_get_sbe32s(f, &env->CP0_Random);
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qemu_get_sbe32s(f, &env->CP0_VPEControl);
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qemu_get_sbe32s(f, &env->CP0_VPEConf0);
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qemu_get_sbe32s(f, &env->CP0_VPEConf1);
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qemu_get_betls(f, &env->CP0_YQMask);
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qemu_get_betls(f, &env->CP0_VPESchedule);
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qemu_get_betls(f, &env->CP0_VPEScheFBack);
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qemu_get_sbe32s(f, &env->CP0_VPEOpt);
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qemu_get_betls(f, &env->CP0_EntryLo0);
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qemu_get_betls(f, &env->CP0_EntryLo1);
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qemu_get_betls(f, &env->CP0_Context);
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qemu_get_sbe32s(f, &env->CP0_PageMask);
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qemu_get_sbe32s(f, &env->CP0_PageGrain);
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qemu_get_sbe32s(f, &env->CP0_Wired);
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qemu_get_sbe32s(f, &env->CP0_SRSConf0);
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qemu_get_sbe32s(f, &env->CP0_SRSConf1);
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qemu_get_sbe32s(f, &env->CP0_SRSConf2);
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qemu_get_sbe32s(f, &env->CP0_SRSConf3);
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qemu_get_sbe32s(f, &env->CP0_SRSConf4);
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qemu_get_sbe32s(f, &env->CP0_HWREna);
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qemu_get_betls(f, &env->CP0_BadVAddr);
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if (version_id >= 5) {
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qemu_get_be32s(f, &env->CP0_BadInstr);
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qemu_get_be32s(f, &env->CP0_BadInstrP);
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}
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qemu_get_sbe32s(f, &env->CP0_Count);
|
||||
qemu_get_betls(f, &env->CP0_EntryHi);
|
||||
qemu_get_sbe32s(f, &env->CP0_Compare);
|
||||
qemu_get_sbe32s(f, &env->CP0_Status);
|
||||
qemu_get_sbe32s(f, &env->CP0_IntCtl);
|
||||
qemu_get_sbe32s(f, &env->CP0_SRSCtl);
|
||||
qemu_get_sbe32s(f, &env->CP0_SRSMap);
|
||||
qemu_get_sbe32s(f, &env->CP0_Cause);
|
||||
qemu_get_betls(f, &env->CP0_EPC);
|
||||
qemu_get_sbe32s(f, &env->CP0_PRid);
|
||||
qemu_get_sbe32s(f, &env->CP0_EBase);
|
||||
qemu_get_sbe32s(f, &env->CP0_Config0);
|
||||
qemu_get_sbe32s(f, &env->CP0_Config1);
|
||||
qemu_get_sbe32s(f, &env->CP0_Config2);
|
||||
qemu_get_sbe32s(f, &env->CP0_Config3);
|
||||
qemu_get_sbe32s(f, &env->CP0_Config6);
|
||||
qemu_get_sbe32s(f, &env->CP0_Config7);
|
||||
qemu_get_betls(f, &env->lladdr);
|
||||
for(i = 0; i < 8; i++)
|
||||
qemu_get_betls(f, &env->CP0_WatchLo[i]);
|
||||
for(i = 0; i < 8; i++)
|
||||
qemu_get_sbe32s(f, &env->CP0_WatchHi[i]);
|
||||
qemu_get_betls(f, &env->CP0_XContext);
|
||||
qemu_get_sbe32s(f, &env->CP0_Framemask);
|
||||
qemu_get_sbe32s(f, &env->CP0_Debug);
|
||||
qemu_get_betls(f, &env->CP0_DEPC);
|
||||
qemu_get_sbe32s(f, &env->CP0_Performance0);
|
||||
qemu_get_sbe32s(f, &env->CP0_TagLo);
|
||||
qemu_get_sbe32s(f, &env->CP0_DataLo);
|
||||
qemu_get_sbe32s(f, &env->CP0_TagHi);
|
||||
qemu_get_sbe32s(f, &env->CP0_DataHi);
|
||||
qemu_get_betls(f, &env->CP0_ErrorEPC);
|
||||
qemu_get_sbe32s(f, &env->CP0_DESAVE);
|
||||
if (version_id >= 5) {
|
||||
for (i = 0; i < MIPS_KSCRATCH_NUM; i++) {
|
||||
qemu_get_betls(f, &env->CP0_KScratch[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Load inactive TC state */
|
||||
for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) {
|
||||
load_tc(f, &env->tcs[i], version_id);
|
||||
}
|
||||
for (i = 0; i < MIPS_FPU_MAX; i++)
|
||||
load_fpu(f, &env->fpus[i]);
|
||||
|
||||
/* XXX: ensure compatibility for halted bit ? */
|
||||
tlb_flush(CPU(cpu), 1);
|
||||
fpr_t *v = pv;
|
||||
qemu_get_be64s(f, &v->d);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void put_fpr(QEMUFile *f, void *pv, size_t size)
|
||||
{
|
||||
fpr_t *v = pv;
|
||||
qemu_put_be64s(f, &v->d);
|
||||
}
|
||||
|
||||
const VMStateInfo vmstate_info_fpr = {
|
||||
.name = "fpr",
|
||||
.get = get_fpr,
|
||||
.put = put_fpr,
|
||||
};
|
||||
|
||||
#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
|
||||
VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
|
||||
|
||||
#define VMSTATE_FPR_ARRAY(_f, _s, _n) \
|
||||
VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
|
||||
|
||||
static VMStateField vmstate_fpu_fields[] = {
|
||||
VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
|
||||
VMSTATE_INT8(fp_status.float_detect_tininess, CPUMIPSFPUContext),
|
||||
VMSTATE_INT8(fp_status.float_rounding_mode, CPUMIPSFPUContext),
|
||||
VMSTATE_INT8(fp_status.float_exception_flags, CPUMIPSFPUContext),
|
||||
VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
|
||||
VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
|
||||
VMSTATE_END_OF_LIST()
|
||||
};
|
||||
|
||||
const VMStateDescription vmstate_fpu = {
|
||||
.name = "cpu/fpu",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = vmstate_fpu_fields
|
||||
};
|
||||
|
||||
const VMStateDescription vmstate_inactive_fpu = {
|
||||
.name = "cpu/inactive_fpu",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = vmstate_fpu_fields
|
||||
};
|
||||
|
||||
/* TC state */
|
||||
|
||||
static VMStateField vmstate_tc_fields[] = {
|
||||
VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
|
||||
VMSTATE_UINTTL(PC, TCState),
|
||||
VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
|
||||
VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
|
||||
VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
|
||||
VMSTATE_UINTTL(DSPControl, TCState),
|
||||
VMSTATE_INT32(CP0_TCStatus, TCState),
|
||||
VMSTATE_INT32(CP0_TCBind, TCState),
|
||||
VMSTATE_UINTTL(CP0_TCHalt, TCState),
|
||||
VMSTATE_UINTTL(CP0_TCContext, TCState),
|
||||
VMSTATE_UINTTL(CP0_TCSchedule, TCState),
|
||||
VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
|
||||
VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
|
||||
VMSTATE_UINTTL(CP0_UserLocal, TCState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
};
|
||||
|
||||
const VMStateDescription vmstate_tc = {
|
||||
.name = "cpu/tc",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = vmstate_tc_fields
|
||||
};
|
||||
|
||||
const VMStateDescription vmstate_inactive_tc = {
|
||||
.name = "cpu/inactive_tc",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = vmstate_tc_fields
|
||||
};
|
||||
|
||||
/* MVP state */
|
||||
|
||||
const VMStateDescription vmstate_mvp = {
|
||||
.name = "cpu/mvp",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
|
||||
VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
|
||||
VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
/* TLB state */
|
||||
|
||||
static int get_tlb(QEMUFile *f, void *pv, size_t size)
|
||||
{
|
||||
r4k_tlb_t *v = pv;
|
||||
uint16_t flags;
|
||||
|
||||
qemu_get_betls(f, &v->VPN);
|
||||
qemu_get_be32s(f, &v->PageMask);
|
||||
qemu_get_8s(f, &v->ASID);
|
||||
qemu_get_be16s(f, &flags);
|
||||
v->G = (flags >> 10) & 1;
|
||||
v->C0 = (flags >> 7) & 3;
|
||||
v->C1 = (flags >> 4) & 3;
|
||||
v->V0 = (flags >> 3) & 1;
|
||||
v->V1 = (flags >> 2) & 1;
|
||||
v->D0 = (flags >> 1) & 1;
|
||||
v->D1 = (flags >> 0) & 1;
|
||||
v->EHINV = (flags >> 15) & 1;
|
||||
v->RI1 = (flags >> 14) & 1;
|
||||
v->RI0 = (flags >> 13) & 1;
|
||||
v->XI1 = (flags >> 12) & 1;
|
||||
v->XI0 = (flags >> 11) & 1;
|
||||
qemu_get_betls(f, &v->PFN[0]);
|
||||
qemu_get_betls(f, &v->PFN[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void put_tlb(QEMUFile *f, void *pv, size_t size)
|
||||
{
|
||||
r4k_tlb_t *v = pv;
|
||||
|
||||
uint16_t flags = ((v->EHINV << 15) |
|
||||
(v->RI1 << 14) |
|
||||
(v->RI0 << 13) |
|
||||
(v->XI1 << 12) |
|
||||
(v->XI0 << 11) |
|
||||
(v->G << 10) |
|
||||
(v->C0 << 7) |
|
||||
(v->C1 << 4) |
|
||||
(v->V0 << 3) |
|
||||
(v->V1 << 2) |
|
||||
(v->D0 << 1) |
|
||||
(v->D1 << 0));
|
||||
|
||||
qemu_put_betls(f, &v->VPN);
|
||||
qemu_put_be32s(f, &v->PageMask);
|
||||
qemu_put_8s(f, &v->ASID);
|
||||
qemu_put_be16s(f, &flags);
|
||||
qemu_put_betls(f, &v->PFN[0]);
|
||||
qemu_put_betls(f, &v->PFN[1]);
|
||||
}
|
||||
|
||||
const VMStateInfo vmstate_info_tlb = {
|
||||
.name = "tlb_entry",
|
||||
.get = get_tlb,
|
||||
.put = put_tlb,
|
||||
};
|
||||
|
||||
#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \
|
||||
VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
|
||||
|
||||
#define VMSTATE_TLB_ARRAY(_f, _s, _n) \
|
||||
VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
|
||||
|
||||
const VMStateDescription vmstate_tlb = {
|
||||
.name = "cpu/tlb",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
|
||||
VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
|
||||
VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
/* MIPS CPU state */
|
||||
|
||||
const VMStateDescription vmstate_mips_cpu = {
|
||||
.name = "cpu",
|
||||
.version_id = 5,
|
||||
.minimum_version_id = 5,
|
||||
.fields = (VMStateField[]) {
|
||||
/* Active TC */
|
||||
VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
|
||||
|
||||
/* Active FPU */
|
||||
VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
|
||||
CPUMIPSFPUContext),
|
||||
|
||||
/* MVP */
|
||||
VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
|
||||
CPUMIPSMVPContext),
|
||||
|
||||
/* TLB */
|
||||
VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
|
||||
CPUMIPSTLBContext),
|
||||
|
||||
/* CPU metastate */
|
||||
VMSTATE_UINT32(env.current_tc, MIPSCPU),
|
||||
VMSTATE_UINT32(env.current_fpu, MIPSCPU),
|
||||
VMSTATE_INT32(env.error_code, MIPSCPU),
|
||||
VMSTATE_UINT32(env.hflags, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.btarget, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.bcond, MIPSCPU),
|
||||
|
||||
/* Remaining CP0 registers */
|
||||
VMSTATE_INT32(env.CP0_Index, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Random, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_EntryLo0, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_EntryLo1, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
|
||||
VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
|
||||
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Status, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_EBase, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.lladdr, MIPSCPU),
|
||||
VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
|
||||
VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
|
||||
VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_TagLo, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
|
||||
VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
|
||||
|
||||
/* Inactive TC */
|
||||
VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
|
||||
vmstate_inactive_tc, TCState),
|
||||
VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
|
||||
vmstate_inactive_fpu, CPUMIPSFPUContext),
|
||||
|
||||
VMSTATE_END_OF_LIST()
|
||||
},
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue