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hw/dma/pl080: Fix bad bit mask (PL080_CONF_M1 | PL080_CONF_M1)
The M1 and M2 bits are both used for configuring the endianness of the AHB master interfaces, so the second PL080_CONF_M1 should be PL080_CONF_M2 instead. Buglink: https://bugs.launchpad.net/qemu/+bug/1631773 Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1476274451-26567-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -351,7 +351,7 @@ static void pl080_write(void *opaque, hwaddr offset,
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break;
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case 12: /* Configuration */
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s->conf = value;
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if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
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if (s->conf & (PL080_CONF_M1 | PL080_CONF_M2)) {
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qemu_log_mask(LOG_UNIMP,
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"pl080_write: Big-endian DMA not implemented\n");
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}
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