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target/ppc: changed ppc_hash64_xlate to use mmu_idx
Changed hash64 address translation to use the supplied mmu_idx instead of using the one stored in the msr, for parity purposes (other book3s MMUs already use it). Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210628133610.1143-4-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Bruno Larsen (billionai)
David Gibson
parent
3f9f76d5bb
commit
03695a9870
3 changed files with 23 additions and 24 deletions
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@ -366,10 +366,9 @@ static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
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}
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/* Check Basic Storage Protection */
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static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
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static int ppc_hash64_pte_prot(int mmu_idx,
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ppc_slb_t *slb, ppc_hash_pte64_t pte)
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{
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CPUPPCState *env = &cpu->env;
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unsigned pp, key;
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/*
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* Some pp bit combinations have undefined behaviour, so default
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@ -377,7 +376,7 @@ static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
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*/
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int prot = 0;
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key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
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key = !!(mmuidx_pr(mmu_idx) ? (slb->vsid & SLB_VSID_KP)
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: (slb->vsid & SLB_VSID_KS));
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pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
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@ -744,17 +743,17 @@ static bool ppc_hash64_use_vrma(CPUPPCState *env)
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}
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}
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static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code)
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static void ppc_hash64_set_isi(CPUState *cs, int mmu_idx, uint64_t error_code)
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{
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CPUPPCState *env = &POWERPC_CPU(cs)->env;
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bool vpm;
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if (msr_ir) {
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if (!mmuidx_real(mmu_idx)) {
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vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
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} else {
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vpm = ppc_hash64_use_vrma(env);
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}
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if (vpm && !msr_hv) {
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if (vpm && !mmuidx_hv(mmu_idx)) {
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cs->exception_index = POWERPC_EXCP_HISI;
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} else {
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cs->exception_index = POWERPC_EXCP_ISI;
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@ -762,17 +761,17 @@ static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code)
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env->error_code = error_code;
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}
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static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr)
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static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t dar, uint64_t dsisr)
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{
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CPUPPCState *env = &POWERPC_CPU(cs)->env;
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bool vpm;
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if (msr_dr) {
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if (!mmuidx_real(mmu_idx)) {
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vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
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} else {
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vpm = ppc_hash64_use_vrma(env);
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}
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if (vpm && !msr_hv) {
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if (vpm && !mmuidx_hv(mmu_idx)) {
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cs->exception_index = POWERPC_EXCP_HDSI;
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env->spr[SPR_HDAR] = dar;
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env->spr[SPR_HDSISR] = dsisr;
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@ -874,7 +873,7 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
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}
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bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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hwaddr *raddrp, int *psizep, int *protp,
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hwaddr *raddrp, int *psizep, int *protp, int mmu_idx,
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bool guest_visible)
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{
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CPUState *cs = CPU(cpu);
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@ -897,7 +896,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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*/
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/* 1. Handle real mode accesses */
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if (access_type == MMU_INST_FETCH ? !msr_ir : !msr_dr) {
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if (mmuidx_real(mmu_idx)) {
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/*
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* Translation is supposedly "off", but in real mode the top 4
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* effective address bits are (mostly) ignored
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@ -909,7 +908,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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* In virtual hypervisor mode, there's nothing to do:
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* EA == GPA == qemu guest address
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*/
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} else if (msr_hv || !env->has_hv_mode) {
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} else if (mmuidx_hv(mmu_idx) || !env->has_hv_mode) {
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/* In HV mode, add HRMOR if top EA bit is clear */
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if (!(eaddr >> 63)) {
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raddr |= env->spr[SPR_HRMOR];
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@ -937,13 +936,13 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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}
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switch (access_type) {
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case MMU_INST_FETCH:
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ppc_hash64_set_isi(cs, SRR1_PROTFAULT);
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ppc_hash64_set_isi(cs, mmu_idx, SRR1_PROTFAULT);
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break;
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case MMU_DATA_LOAD:
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ppc_hash64_set_dsi(cs, eaddr, DSISR_PROTFAULT);
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ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_PROTFAULT);
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break;
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case MMU_DATA_STORE:
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ppc_hash64_set_dsi(cs, eaddr,
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ppc_hash64_set_dsi(cs, mmu_idx, eaddr,
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DSISR_PROTFAULT | DSISR_ISSTORE);
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break;
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default:
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@ -996,7 +995,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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/* 3. Check for segment level no-execute violation */
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if (access_type == MMU_INST_FETCH && (slb->vsid & SLB_VSID_N)) {
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if (guest_visible) {
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ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD);
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ppc_hash64_set_isi(cs, mmu_idx, SRR1_NOEXEC_GUARD);
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}
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return false;
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}
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@ -1009,13 +1008,13 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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}
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switch (access_type) {
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case MMU_INST_FETCH:
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ppc_hash64_set_isi(cs, SRR1_NOPTE);
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ppc_hash64_set_isi(cs, mmu_idx, SRR1_NOPTE);
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break;
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case MMU_DATA_LOAD:
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ppc_hash64_set_dsi(cs, eaddr, DSISR_NOPTE);
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ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_NOPTE);
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break;
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case MMU_DATA_STORE:
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ppc_hash64_set_dsi(cs, eaddr, DSISR_NOPTE | DSISR_ISSTORE);
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ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_NOPTE | DSISR_ISSTORE);
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break;
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default:
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g_assert_not_reached();
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@ -1028,7 +1027,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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/* 5. Check access permissions */
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exec_prot = ppc_hash64_pte_noexec_guard(cpu, pte);
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pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
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pp_prot = ppc_hash64_pte_prot(mmu_idx, slb, pte);
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amr_prot = ppc_hash64_amr_prot(cpu, pte);
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prot = exec_prot & pp_prot & amr_prot;
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@ -1049,7 +1048,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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if (PAGE_EXEC & ~amr_prot) {
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srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */
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}
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ppc_hash64_set_isi(cs, srr1);
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ppc_hash64_set_isi(cs, mmu_idx, srr1);
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} else {
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int dsisr = 0;
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if (need_prot & ~pp_prot) {
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@ -1061,7 +1060,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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if (need_prot & ~amr_prot) {
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dsisr |= DSISR_AMR;
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}
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ppc_hash64_set_dsi(cs, eaddr, dsisr);
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ppc_hash64_set_dsi(cs, mmu_idx, eaddr, dsisr);
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}
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return false;
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}
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@ -8,7 +8,7 @@ void dump_slb(PowerPCCPU *cpu);
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int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
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target_ulong esid, target_ulong vsid);
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bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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hwaddr *raddrp, int *psizep, int *protp,
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hwaddr *raddrp, int *psizep, int *protp, int mmu_idx,
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bool guest_visible);
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void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
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target_ulong pte_index,
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@ -2908,7 +2908,7 @@ static bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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case POWERPC_MMU_2_06:
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case POWERPC_MMU_2_07:
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return ppc_hash64_xlate(cpu, eaddr, access_type,
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raddrp, psizep, protp, guest_visible);
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raddrp, psizep, protp, mmu_idx, guest_visible);
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#endif
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case POWERPC_MMU_32B:
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