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https://github.com/torvalds/linux
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feb24691e3
All drivers use the same values for TSF sync, this will move the value determination into rt2x00config.c, and the definition for the values to rt2x00reg.h Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
293 lines
7.1 KiB
C
293 lines
7.1 KiB
C
/*
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Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
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<http://rt2x00.serialmonkey.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the
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Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/*
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Module: rt2x00
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Abstract: rt2x00 generic register information.
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*/
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#ifndef RT2X00REG_H
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#define RT2X00REG_H
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/*
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* TX result flags.
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*/
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enum TX_STATUS {
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TX_SUCCESS = 0,
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TX_SUCCESS_RETRY = 1,
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TX_FAIL_RETRY = 2,
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TX_FAIL_INVALID = 3,
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TX_FAIL_OTHER = 4,
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};
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/*
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* Antenna values
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*/
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enum antenna {
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ANTENNA_SW_DIVERSITY = 0,
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ANTENNA_A = 1,
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ANTENNA_B = 2,
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ANTENNA_HW_DIVERSITY = 3,
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};
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/*
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* Led mode values.
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*/
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enum led_mode {
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LED_MODE_DEFAULT = 0,
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LED_MODE_TXRX_ACTIVITY = 1,
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LED_MODE_SIGNAL_STRENGTH = 2,
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LED_MODE_ASUS = 3,
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LED_MODE_ALPHA = 4,
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};
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/*
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* TSF sync values
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*/
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enum tsf_sync {
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TSF_SYNC_NONE = 0,
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TSF_SYNC_INFRA = 1,
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TSF_SYNC_BEACON = 2,
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};
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/*
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* Device states
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*/
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enum dev_state {
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STATE_DEEP_SLEEP = 0,
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STATE_SLEEP = 1,
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STATE_STANDBY = 2,
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STATE_AWAKE = 3,
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/*
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* Additional device states, these values are
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* not strict since they are not directly passed
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* into the device.
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*/
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STATE_RADIO_ON,
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STATE_RADIO_OFF,
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STATE_RADIO_RX_ON,
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STATE_RADIO_RX_OFF,
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STATE_RADIO_IRQ_ON,
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STATE_RADIO_IRQ_OFF,
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};
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/*
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* IFS backoff values
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*/
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enum ifs {
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IFS_BACKOFF = 0,
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IFS_SIFS = 1,
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IFS_NEW_BACKOFF = 2,
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IFS_NONE = 3,
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};
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/*
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* Cipher types for hardware encryption
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*/
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enum cipher {
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CIPHER_NONE = 0,
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CIPHER_WEP64 = 1,
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CIPHER_WEP128 = 2,
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CIPHER_TKIP = 3,
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CIPHER_AES = 4,
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/*
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* The following fields were added by rt61pci and rt73usb.
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*/
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CIPHER_CKIP64 = 5,
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CIPHER_CKIP128 = 6,
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CIPHER_TKIP_NO_MIC = 7,
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};
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/*
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* Register handlers.
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* We store the position of a register field inside a field structure,
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* This will simplify the process of setting and reading a certain field
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* inside the register while making sure the process remains byte order safe.
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*/
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struct rt2x00_field8 {
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u8 bit_offset;
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u8 bit_mask;
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};
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struct rt2x00_field16 {
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u16 bit_offset;
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u16 bit_mask;
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};
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struct rt2x00_field32 {
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u32 bit_offset;
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u32 bit_mask;
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};
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/*
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* Power of two check, this will check
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* if the mask that has been given contains
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* and contiguous set of bits.
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*/
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#define is_power_of_two(x) ( !((x) & ((x)-1)) )
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#define low_bit_mask(x) ( ((x)-1) & ~(x) )
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#define is_valid_mask(x) is_power_of_two(1 + (x) + low_bit_mask(x))
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#define FIELD8(__mask) \
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({ \
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BUILD_BUG_ON(!(__mask) || \
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!is_valid_mask(__mask) || \
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(__mask) != (u8)(__mask)); \
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(struct rt2x00_field8) { \
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__ffs(__mask), (__mask) \
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}; \
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})
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#define FIELD16(__mask) \
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({ \
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BUILD_BUG_ON(!(__mask) || \
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!is_valid_mask(__mask) || \
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(__mask) != (u16)(__mask));\
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(struct rt2x00_field16) { \
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__ffs(__mask), (__mask) \
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}; \
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})
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#define FIELD32(__mask) \
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({ \
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BUILD_BUG_ON(!(__mask) || \
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!is_valid_mask(__mask) || \
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(__mask) != (u32)(__mask));\
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(struct rt2x00_field32) { \
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__ffs(__mask), (__mask) \
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}; \
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})
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static inline void rt2x00_set_field32(u32 *reg,
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const struct rt2x00_field32 field,
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const u32 value)
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{
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*reg &= ~(field.bit_mask);
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*reg |= (value << field.bit_offset) & field.bit_mask;
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}
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static inline u32 rt2x00_get_field32(const u32 reg,
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const struct rt2x00_field32 field)
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{
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return (reg & field.bit_mask) >> field.bit_offset;
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}
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static inline void rt2x00_set_field16(u16 *reg,
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const struct rt2x00_field16 field,
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const u16 value)
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{
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*reg &= ~(field.bit_mask);
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*reg |= (value << field.bit_offset) & field.bit_mask;
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}
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static inline u16 rt2x00_get_field16(const u16 reg,
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const struct rt2x00_field16 field)
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{
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return (reg & field.bit_mask) >> field.bit_offset;
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}
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static inline void rt2x00_set_field8(u8 *reg,
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const struct rt2x00_field8 field,
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const u8 value)
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{
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*reg &= ~(field.bit_mask);
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*reg |= (value << field.bit_offset) & field.bit_mask;
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}
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static inline u8 rt2x00_get_field8(const u8 reg,
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const struct rt2x00_field8 field)
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{
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return (reg & field.bit_mask) >> field.bit_offset;
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}
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/*
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* Device specific rate value.
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* We will have to create the device specific rate value
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* passed to the ieee80211 kernel. We need to make it a consist of
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* multiple fields because we want to store more then 1 device specific
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* values inside the value.
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* 1 - rate, stored as 100 kbit/s.
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* 2 - preamble, short_preamble enabled flag.
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* 3 - MASK_RATE, which rates are enabled in this mode, this mask
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* corresponds with the TX register format for the current device.
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* 4 - plcp, 802.11b rates are device specific,
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* 802.11g rates are set according to the ieee802.11a-1999 p.14.
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* The bit to enable preamble is set in a seperate define.
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*/
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#define DEV_RATE FIELD32(0x000007ff)
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#define DEV_PREAMBLE FIELD32(0x00000800)
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#define DEV_RATEMASK FIELD32(0x00fff000)
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#define DEV_PLCP FIELD32(0xff000000)
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/*
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* Bitfields
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*/
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#define DEV_RATEBIT_1MB ( 1 << 0 )
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#define DEV_RATEBIT_2MB ( 1 << 1 )
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#define DEV_RATEBIT_5_5MB ( 1 << 2 )
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#define DEV_RATEBIT_11MB ( 1 << 3 )
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#define DEV_RATEBIT_6MB ( 1 << 4 )
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#define DEV_RATEBIT_9MB ( 1 << 5 )
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#define DEV_RATEBIT_12MB ( 1 << 6 )
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#define DEV_RATEBIT_18MB ( 1 << 7 )
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#define DEV_RATEBIT_24MB ( 1 << 8 )
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#define DEV_RATEBIT_36MB ( 1 << 9 )
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#define DEV_RATEBIT_48MB ( 1 << 10 )
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#define DEV_RATEBIT_54MB ( 1 << 11 )
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/*
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* Bitmasks for DEV_RATEMASK
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*/
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#define DEV_RATEMASK_1MB ( (DEV_RATEBIT_1MB << 1) -1 )
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#define DEV_RATEMASK_2MB ( (DEV_RATEBIT_2MB << 1) -1 )
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#define DEV_RATEMASK_5_5MB ( (DEV_RATEBIT_5_5MB << 1) -1 )
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#define DEV_RATEMASK_11MB ( (DEV_RATEBIT_11MB << 1) -1 )
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#define DEV_RATEMASK_6MB ( (DEV_RATEBIT_6MB << 1) -1 )
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#define DEV_RATEMASK_9MB ( (DEV_RATEBIT_9MB << 1) -1 )
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#define DEV_RATEMASK_12MB ( (DEV_RATEBIT_12MB << 1) -1 )
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#define DEV_RATEMASK_18MB ( (DEV_RATEBIT_18MB << 1) -1 )
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#define DEV_RATEMASK_24MB ( (DEV_RATEBIT_24MB << 1) -1 )
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#define DEV_RATEMASK_36MB ( (DEV_RATEBIT_36MB << 1) -1 )
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#define DEV_RATEMASK_48MB ( (DEV_RATEBIT_48MB << 1) -1 )
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#define DEV_RATEMASK_54MB ( (DEV_RATEBIT_54MB << 1) -1 )
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/*
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* Bitmask groups of bitrates
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*/
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#define DEV_BASIC_RATEMASK \
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( DEV_RATEMASK_11MB | \
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DEV_RATEBIT_6MB | DEV_RATEBIT_12MB | DEV_RATEBIT_24MB )
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#define DEV_CCK_RATEMASK ( DEV_RATEMASK_11MB )
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#define DEV_OFDM_RATEMASK ( DEV_RATEMASK_54MB & ~DEV_CCK_RATEMASK )
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/*
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* Macro's to set and get specific fields from the device specific val and val2
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* fields inside the ieee80211_rate entry.
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*/
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#define DEVICE_SET_RATE_FIELD(__value, __mask) \
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(int)( ((__value) << DEV_##__mask.bit_offset) & DEV_##__mask.bit_mask )
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#define DEVICE_GET_RATE_FIELD(__value, __mask) \
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(int)( ((__value) & DEV_##__mask.bit_mask) >> DEV_##__mask.bit_offset )
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#endif /* RT2X00REG_H */
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