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https://github.com/torvalds/linux
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5f1f3d5088
The ranges DT entry needed by the PCIe controller is defined at the SoC .dtsi level. However, some boards have a NOR flash, and to support it, they need to override the SoC-level ranges property to add an additional range. Since PCIe and NOR support came separately, some boards were not properly changed to include the PCIe range in their ranges property at the .dts level. This commit fixes those platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
188 lines
3.7 KiB
Plaintext
188 lines
3.7 KiB
Plaintext
/*
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* Device Tree file for OpenBlocks AX3-4 board
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*
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* Copyright (C) 2012 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/include/ "armada-xp-mv78260.dtsi"
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/ {
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model = "PlatHome OpenBlocks AX3-4 board";
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compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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memory {
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device_type = "memory";
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reg = <0 0x00000000 0 0xC0000000>; /* 3 GB */
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};
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soc {
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ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
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0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
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0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>;
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internal-regs {
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serial@12000 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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serial@12100 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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pinctrl {
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led_pins: led-pins-0 {
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marvell,pins = "mpp49", "mpp51", "mpp53";
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marvell,function = "gpio";
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&led_pins>;
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red_led {
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label = "red_led";
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gpios = <&gpio1 17 1>;
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default-state = "off";
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};
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yellow_led {
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label = "yellow_led";
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gpios = <&gpio1 19 1>;
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default-state = "off";
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};
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green_led {
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label = "green_led";
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gpios = <&gpio1 21 1>;
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default-state = "off";
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linux,default-trigger = "heartbeat";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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button@1 {
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label = "Init Button";
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linux,code = <116>;
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gpios = <&gpio1 28 0>;
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};
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};
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mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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};
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};
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ethernet@70000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "sgmii";
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};
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ethernet@74000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "sgmii";
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};
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ethernet@30000 {
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status = "okay";
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phy = <&phy2>;
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phy-mode = "sgmii";
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};
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ethernet@34000 {
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status = "okay";
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phy = <&phy3>;
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phy-mode = "sgmii";
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};
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i2c@11000 {
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status = "okay";
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clock-frequency = <400000>;
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};
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i2c@11100 {
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status = "okay";
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clock-frequency = <400000>;
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s35390a: s35390a@30 {
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compatible = "s35390a";
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reg = <0x30>;
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};
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};
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sata@a0000 {
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nr-ports = <2>;
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status = "okay";
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};
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usb@50000 {
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status = "okay";
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};
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usb@51000 {
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status = "okay";
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};
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devbus-bootcs@10400 {
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status = "okay";
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ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
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/* Device Bus parameters are required */
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/* Read parameters */
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devbus,bus-width = <8>;
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devbus,turn-off-ps = <60000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <124000>;
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devbus,acc-next-ps = <248000>;
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devbus,rd-setup-ps = <0>;
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devbus,rd-hold-ps = <0>;
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/* Write parameters */
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devbus,sync-enable = <0>;
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devbus,wr-high-ps = <60000>;
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devbus,wr-low-ps = <60000>;
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devbus,ale-wr-ps = <60000>;
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/* NOR 128 MiB */
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nor@0 {
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compatible = "cfi-flash";
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reg = <0 0x8000000>;
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bank-width = <2>;
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};
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};
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pcie-controller {
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status = "okay";
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/* Internal mini-PCIe connector */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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};
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};
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};
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};
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