mirror of
https://github.com/torvalds/linux
synced 2024-10-27 13:48:49 +00:00
aa58c40563
Again, doesn't quite match NVIDIA's, but not sure it really matters. This will however, match the same rules we use to calculate the other related grctx magics. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
797 lines
22 KiB
C
797 lines
22 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <linux/firmware.h>
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_mm.h"
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#include "nvc0_graph.h"
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static int
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nvc0_graph_load_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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nv_wr32(dev, 0x409840, 0x00000030);
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nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
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nv_wr32(dev, 0x409504, 0x00000003);
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if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
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NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
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return 0;
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}
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static int
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nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
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{
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nv_wr32(dev, 0x409840, 0x00000003);
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nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
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nv_wr32(dev, 0x409504, 0x00000009);
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if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
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return -EBUSY;
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}
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return 0;
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}
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static int
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nvc0_graph_construct_context(struct nouveau_channel *chan)
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{
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struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
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struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
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struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
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struct drm_device *dev = chan->dev;
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int ret, i;
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u32 *ctx;
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ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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nvc0_graph_load_context(chan);
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nv_wo32(grch->grctx, 0x1c, 1);
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nv_wo32(grch->grctx, 0x20, 0);
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nv_wo32(grch->grctx, 0x28, 0);
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nv_wo32(grch->grctx, 0x2c, 0);
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dev_priv->engine.instmem.flush(dev);
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ret = nvc0_grctx_generate(chan);
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if (ret) {
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kfree(ctx);
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return ret;
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}
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ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
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if (ret) {
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kfree(ctx);
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return ret;
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}
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for (i = 0; i < priv->grctx_size; i += 4)
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ctx[i / 4] = nv_ro32(grch->grctx, i);
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priv->grctx_vals = ctx;
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return 0;
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}
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static int
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nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
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{
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struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
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struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
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struct drm_device *dev = chan->dev;
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int i = 0, gpc, tp, ret;
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u32 magic;
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ret = nouveau_gpuobj_new(dev, NULL, 0x2000, 256, NVOBJ_FLAG_VM,
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&grch->unk408004);
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if (ret)
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return ret;
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ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 256, NVOBJ_FLAG_VM,
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&grch->unk40800c);
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if (ret)
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return ret;
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ret = nouveau_gpuobj_new(dev, NULL, 384 * 1024, 4096,
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NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER,
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&grch->unk418810);
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if (ret)
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return ret;
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ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0, NVOBJ_FLAG_VM,
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&grch->mmio);
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if (ret)
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return ret;
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nv_wo32(grch->mmio, i++ * 4, 0x00408004);
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nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
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nv_wo32(grch->mmio, i++ * 4, 0x00408008);
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nv_wo32(grch->mmio, i++ * 4, 0x80000018);
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nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
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nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
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nv_wo32(grch->mmio, i++ * 4, 0x00408010);
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nv_wo32(grch->mmio, i++ * 4, 0x80000000);
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nv_wo32(grch->mmio, i++ * 4, 0x00418810);
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nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->vinst >> 12);
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nv_wo32(grch->mmio, i++ * 4, 0x00419848);
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nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->vinst >> 12);
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nv_wo32(grch->mmio, i++ * 4, 0x00419004);
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nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
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nv_wo32(grch->mmio, i++ * 4, 0x00419008);
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nv_wo32(grch->mmio, i++ * 4, 0x00000000);
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nv_wo32(grch->mmio, i++ * 4, 0x00418808);
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nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
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nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
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nv_wo32(grch->mmio, i++ * 4, 0x80000018);
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magic = 0x02180000;
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nv_wo32(grch->mmio, i++ * 4, 0x00405830);
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nv_wo32(grch->mmio, i++ * 4, magic);
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for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
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for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x02fc) {
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u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);
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nv_wo32(grch->mmio, i++ * 4, reg);
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nv_wo32(grch->mmio, i++ * 4, magic);
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}
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}
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grch->mmio_nr = i / 2;
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return 0;
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}
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static int
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nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
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struct nvc0_graph_priv *priv = nv_engine(dev, engine);
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struct nvc0_graph_chan *grch;
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struct nouveau_gpuobj *grctx;
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int ret, i;
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grch = kzalloc(sizeof(*grch), GFP_KERNEL);
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if (!grch)
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return -ENOMEM;
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chan->engctx[NVOBJ_ENGINE_GR] = grch;
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ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256,
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NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
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&grch->grctx);
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if (ret)
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goto error;
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grctx = grch->grctx;
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ret = nvc0_graph_create_context_mmio_list(chan);
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if (ret)
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goto error;
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nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->vinst) | 4);
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nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->vinst));
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pinstmem->flush(dev);
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if (!priv->grctx_vals) {
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ret = nvc0_graph_construct_context(chan);
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if (ret)
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goto error;
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}
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for (i = 0; i < priv->grctx_size; i += 4)
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nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
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nv_wo32(grctx, 0xf4, 0);
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nv_wo32(grctx, 0xf8, 0);
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nv_wo32(grctx, 0x10, grch->mmio_nr);
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nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst));
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nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst));
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nv_wo32(grctx, 0x1c, 1);
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nv_wo32(grctx, 0x20, 0);
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nv_wo32(grctx, 0x28, 0);
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nv_wo32(grctx, 0x2c, 0);
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pinstmem->flush(dev);
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return 0;
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error:
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priv->base.context_del(chan, engine);
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return ret;
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}
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static void
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nvc0_graph_context_del(struct nouveau_channel *chan, int engine)
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{
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struct nvc0_graph_chan *grch = chan->engctx[engine];
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nouveau_gpuobj_ref(NULL, &grch->mmio);
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nouveau_gpuobj_ref(NULL, &grch->unk418810);
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nouveau_gpuobj_ref(NULL, &grch->unk40800c);
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nouveau_gpuobj_ref(NULL, &grch->unk408004);
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nouveau_gpuobj_ref(NULL, &grch->grctx);
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chan->engctx[engine] = NULL;
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}
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static int
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nvc0_graph_object_new(struct nouveau_channel *chan, int engine,
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u32 handle, u16 class)
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{
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return 0;
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}
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static int
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nvc0_graph_fini(struct drm_device *dev, int engine)
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{
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return 0;
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}
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static int
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nvc0_graph_mthd_page_flip(struct nouveau_channel *chan,
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u32 class, u32 mthd, u32 data)
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{
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nouveau_finish_page_flip(chan, NULL);
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return 0;
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}
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static void
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nvc0_graph_init_obj418880(struct drm_device *dev)
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{
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struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
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int i;
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nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
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nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
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for (i = 0; i < 4; i++)
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nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
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nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
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nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
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}
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static void
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nvc0_graph_init_regs(struct drm_device *dev)
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{
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nv_wr32(dev, 0x400080, 0x003083c2);
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nv_wr32(dev, 0x400088, 0x00006fe7);
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nv_wr32(dev, 0x40008c, 0x00000000);
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nv_wr32(dev, 0x400090, 0x00000030);
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nv_wr32(dev, 0x40013c, 0x013901f7);
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nv_wr32(dev, 0x400140, 0x00000100);
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nv_wr32(dev, 0x400144, 0x00000000);
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nv_wr32(dev, 0x400148, 0x00000110);
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nv_wr32(dev, 0x400138, 0x00000000);
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nv_wr32(dev, 0x400130, 0x00000000);
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nv_wr32(dev, 0x400134, 0x00000000);
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nv_wr32(dev, 0x400124, 0x00000002);
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}
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static void
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nvc0_graph_init_gpc_0(struct drm_device *dev)
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{
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struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
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u32 data[TP_MAX / 8];
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u8 tpnr[GPC_MAX];
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int i, gpc, tpc;
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/*
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* TP ROP UNKVAL(magic_not_rop_nr)
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* 450: 4/0/0/0 2 3
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* 460: 3/4/0/0 4 1
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* 465: 3/4/4/0 4 7
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* 470: 3/3/4/4 5 5
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* 480: 3/4/4/4 6 6
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*
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* magicgpc918
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* 450: 00200000 00000000001000000000000000000000
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* 460: 00124925 00000000000100100100100100100101
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* 465: 000ba2e9 00000000000010111010001011101001
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* 470: 00092493 00000000000010010010010010010011
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* 480: 00088889 00000000000010001000100010001001
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*/
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memset(data, 0x00, sizeof(data));
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memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
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for (i = 0, gpc = -1; i < priv->tp_total; i++) {
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do {
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gpc = (gpc + 1) % priv->gpc_nr;
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} while (!tpnr[gpc]);
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tpc = priv->tp_nr[gpc] - tpnr[gpc]--;
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data[i / 8] |= tpc << ((i % 8) * 4);
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}
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nv_wr32(dev, GPC_BCAST(0x0980), data[0]);
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nv_wr32(dev, GPC_BCAST(0x0984), data[1]);
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nv_wr32(dev, GPC_BCAST(0x0988), data[2]);
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nv_wr32(dev, GPC_BCAST(0x098c), data[3]);
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for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
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nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
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priv->tp_nr[gpc]);
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nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
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nv_wr32(dev, GPC_UNIT(gpc, 0x0918), priv->magicgpc918);
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}
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nv_wr32(dev, GPC_BCAST(0x1bd4), priv->magicgpc918);
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nv_wr32(dev, GPC_BCAST(0x08ac), priv->rop_nr);
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}
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static void
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nvc0_graph_init_units(struct drm_device *dev)
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{
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nv_wr32(dev, 0x409c24, 0x000f0000);
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nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
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nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
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nv_wr32(dev, 0x408030, 0xc0000000);
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nv_wr32(dev, 0x40601c, 0xc0000000);
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nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
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nv_wr32(dev, 0x406018, 0xc0000000);
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nv_wr32(dev, 0x405840, 0xc0000000);
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nv_wr32(dev, 0x405844, 0x00ffffff);
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nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
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nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
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}
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static void
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nvc0_graph_init_gpc_1(struct drm_device *dev)
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{
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struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
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int gpc, tp;
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for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
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nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
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nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
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nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
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nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
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for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
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nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
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nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
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nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
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nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
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nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
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nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe);
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nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f);
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}
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nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
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nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
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}
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}
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static void
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nvc0_graph_init_rop(struct drm_device *dev)
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{
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struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
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int rop;
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for (rop = 0; rop < priv->rop_nr; rop++) {
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nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
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nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
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nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
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nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
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}
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}
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static void
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nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base,
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struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
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{
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int i;
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nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
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for (i = 0; i < data->size / 4; i++)
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nv_wr32(dev, fuc_base + 0x01c4, data->data[i]);
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nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
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for (i = 0; i < code->size / 4; i++) {
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if ((i & 0x3f) == 0)
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nv_wr32(dev, fuc_base + 0x0188, i >> 6);
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nv_wr32(dev, fuc_base + 0x0184, code->data[i]);
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}
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}
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static int
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nvc0_graph_init_ctxctl(struct drm_device *dev)
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{
|
|
struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
|
|
u32 r000260;
|
|
|
|
/* load fuc microcode */
|
|
r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
|
|
nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c, &priv->fuc409d);
|
|
nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac, &priv->fuc41ad);
|
|
nv_wr32(dev, 0x000260, r000260);
|
|
|
|
/* start both of them running */
|
|
nv_wr32(dev, 0x409840, 0xffffffff);
|
|
nv_wr32(dev, 0x41a10c, 0x00000000);
|
|
nv_wr32(dev, 0x40910c, 0x00000000);
|
|
nv_wr32(dev, 0x41a100, 0x00000002);
|
|
nv_wr32(dev, 0x409100, 0x00000002);
|
|
if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
|
|
NV_INFO(dev, "0x409800 wait failed\n");
|
|
|
|
nv_wr32(dev, 0x409840, 0xffffffff);
|
|
nv_wr32(dev, 0x409500, 0x7fffffff);
|
|
nv_wr32(dev, 0x409504, 0x00000021);
|
|
|
|
nv_wr32(dev, 0x409840, 0xffffffff);
|
|
nv_wr32(dev, 0x409500, 0x00000000);
|
|
nv_wr32(dev, 0x409504, 0x00000010);
|
|
if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
|
|
NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
|
|
return -EBUSY;
|
|
}
|
|
priv->grctx_size = nv_rd32(dev, 0x409800);
|
|
|
|
nv_wr32(dev, 0x409840, 0xffffffff);
|
|
nv_wr32(dev, 0x409500, 0x00000000);
|
|
nv_wr32(dev, 0x409504, 0x00000016);
|
|
if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
|
|
NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
nv_wr32(dev, 0x409840, 0xffffffff);
|
|
nv_wr32(dev, 0x409500, 0x00000000);
|
|
nv_wr32(dev, 0x409504, 0x00000025);
|
|
if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
|
|
NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nvc0_graph_init(struct drm_device *dev, int engine)
|
|
{
|
|
int ret;
|
|
|
|
nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
|
|
nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
|
|
|
|
nvc0_graph_init_obj418880(dev);
|
|
nvc0_graph_init_regs(dev);
|
|
/*nvc0_graph_init_unitplemented_magics(dev);*/
|
|
nvc0_graph_init_gpc_0(dev);
|
|
/*nvc0_graph_init_unitplemented_c242(dev);*/
|
|
|
|
nv_wr32(dev, 0x400500, 0x00010001);
|
|
nv_wr32(dev, 0x400100, 0xffffffff);
|
|
nv_wr32(dev, 0x40013c, 0xffffffff);
|
|
|
|
nvc0_graph_init_units(dev);
|
|
nvc0_graph_init_gpc_1(dev);
|
|
nvc0_graph_init_rop(dev);
|
|
|
|
nv_wr32(dev, 0x400108, 0xffffffff);
|
|
nv_wr32(dev, 0x400138, 0xffffffff);
|
|
nv_wr32(dev, 0x400118, 0xffffffff);
|
|
nv_wr32(dev, 0x400130, 0xffffffff);
|
|
nv_wr32(dev, 0x40011c, 0xffffffff);
|
|
nv_wr32(dev, 0x400134, 0xffffffff);
|
|
nv_wr32(dev, 0x400054, 0x34ce3464);
|
|
|
|
ret = nvc0_graph_init_ctxctl(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nouveau_channel *chan;
|
|
unsigned long flags;
|
|
int i;
|
|
|
|
spin_lock_irqsave(&dev_priv->channels.lock, flags);
|
|
for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
|
|
chan = dev_priv->channels.ptr[i];
|
|
if (!chan || !chan->ramin)
|
|
continue;
|
|
|
|
if (inst == chan->ramin->vinst)
|
|
break;
|
|
}
|
|
spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
|
|
return i;
|
|
}
|
|
|
|
static void
|
|
nvc0_graph_isr(struct drm_device *dev)
|
|
{
|
|
u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
|
|
u32 chid = nvc0_graph_isr_chid(dev, inst);
|
|
u32 stat = nv_rd32(dev, 0x400100);
|
|
u32 addr = nv_rd32(dev, 0x400704);
|
|
u32 mthd = (addr & 0x00003ffc);
|
|
u32 subc = (addr & 0x00070000) >> 16;
|
|
u32 data = nv_rd32(dev, 0x400708);
|
|
u32 code = nv_rd32(dev, 0x400110);
|
|
u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
|
|
|
|
if (stat & 0x00000010) {
|
|
if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
|
|
NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
|
|
"subc %d class 0x%04x mthd 0x%04x "
|
|
"data 0x%08x\n",
|
|
chid, inst, subc, class, mthd, data);
|
|
}
|
|
nv_wr32(dev, 0x400100, 0x00000010);
|
|
stat &= ~0x00000010;
|
|
}
|
|
|
|
if (stat & 0x00000020) {
|
|
NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
|
|
"class 0x%04x mthd 0x%04x data 0x%08x\n",
|
|
chid, inst, subc, class, mthd, data);
|
|
nv_wr32(dev, 0x400100, 0x00000020);
|
|
stat &= ~0x00000020;
|
|
}
|
|
|
|
if (stat & 0x00100000) {
|
|
NV_INFO(dev, "PGRAPH: DATA_ERROR [");
|
|
nouveau_enum_print(nv50_data_error_names, code);
|
|
printk("] ch %d [0x%010llx] subc %d class 0x%04x "
|
|
"mthd 0x%04x data 0x%08x\n",
|
|
chid, inst, subc, class, mthd, data);
|
|
nv_wr32(dev, 0x400100, 0x00100000);
|
|
stat &= ~0x00100000;
|
|
}
|
|
|
|
if (stat & 0x00200000) {
|
|
u32 trap = nv_rd32(dev, 0x400108);
|
|
NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
|
|
nv_wr32(dev, 0x400108, trap);
|
|
nv_wr32(dev, 0x400100, 0x00200000);
|
|
stat &= ~0x00200000;
|
|
}
|
|
|
|
if (stat & 0x00080000) {
|
|
u32 ustat = nv_rd32(dev, 0x409c18);
|
|
|
|
NV_INFO(dev, "PGRAPH: CTXCTRL ustat 0x%08x\n", ustat);
|
|
|
|
nv_wr32(dev, 0x409c20, ustat);
|
|
nv_wr32(dev, 0x400100, 0x00080000);
|
|
stat &= ~0x00080000;
|
|
}
|
|
|
|
if (stat) {
|
|
NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
|
|
nv_wr32(dev, 0x400100, stat);
|
|
}
|
|
|
|
nv_wr32(dev, 0x400500, 0x00010001);
|
|
}
|
|
|
|
static void
|
|
nvc0_runk140_isr(struct drm_device *dev)
|
|
{
|
|
u32 units = nv_rd32(dev, 0x00017c) & 0x1f;
|
|
|
|
while (units) {
|
|
u32 unit = ffs(units) - 1;
|
|
u32 reg = 0x140000 + unit * 0x2000;
|
|
u32 st0 = nv_mask(dev, reg + 0x1020, 0, 0);
|
|
u32 st1 = nv_mask(dev, reg + 0x1420, 0, 0);
|
|
|
|
NV_INFO(dev, "PRUNK140: %d 0x%08x 0x%08x\n", unit, st0, st1);
|
|
units &= ~(1 << unit);
|
|
}
|
|
}
|
|
|
|
static int
|
|
nvc0_graph_create_fw(struct drm_device *dev, const char *fwname,
|
|
struct nvc0_graph_fuc *fuc)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
const struct firmware *fw;
|
|
char f[32];
|
|
int ret;
|
|
|
|
snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname);
|
|
ret = request_firmware(&fw, f, &dev->pdev->dev);
|
|
if (ret) {
|
|
snprintf(f, sizeof(f), "nouveau/%s", fwname);
|
|
ret = request_firmware(&fw, f, &dev->pdev->dev);
|
|
if (ret) {
|
|
NV_ERROR(dev, "failed to load %s\n", fwname);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
fuc->size = fw->size;
|
|
fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
|
|
release_firmware(fw);
|
|
return (fuc->data != NULL) ? 0 : -ENOMEM;
|
|
}
|
|
|
|
static void
|
|
nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc)
|
|
{
|
|
if (fuc->data) {
|
|
kfree(fuc->data);
|
|
fuc->data = NULL;
|
|
}
|
|
}
|
|
|
|
static void
|
|
nvc0_graph_destroy(struct drm_device *dev, int engine)
|
|
{
|
|
struct nvc0_graph_priv *priv = nv_engine(dev, engine);
|
|
|
|
nvc0_graph_destroy_fw(&priv->fuc409c);
|
|
nvc0_graph_destroy_fw(&priv->fuc409d);
|
|
nvc0_graph_destroy_fw(&priv->fuc41ac);
|
|
nvc0_graph_destroy_fw(&priv->fuc41ad);
|
|
|
|
nouveau_irq_unregister(dev, 12);
|
|
nouveau_irq_unregister(dev, 25);
|
|
|
|
nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
|
|
nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
|
|
|
|
if (priv->grctx_vals)
|
|
kfree(priv->grctx_vals);
|
|
|
|
NVOBJ_ENGINE_DEL(dev, GR);
|
|
kfree(priv);
|
|
}
|
|
|
|
int
|
|
nvc0_graph_create(struct drm_device *dev)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nvc0_graph_priv *priv;
|
|
int ret, gpc, i;
|
|
|
|
switch (dev_priv->chipset) {
|
|
case 0xc0:
|
|
case 0xc3:
|
|
case 0xc4:
|
|
break;
|
|
default:
|
|
NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
|
|
return 0;
|
|
}
|
|
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->base.destroy = nvc0_graph_destroy;
|
|
priv->base.init = nvc0_graph_init;
|
|
priv->base.fini = nvc0_graph_fini;
|
|
priv->base.context_new = nvc0_graph_context_new;
|
|
priv->base.context_del = nvc0_graph_context_del;
|
|
priv->base.object_new = nvc0_graph_object_new;
|
|
|
|
NVOBJ_ENGINE_ADD(dev, GR, &priv->base);
|
|
nouveau_irq_register(dev, 12, nvc0_graph_isr);
|
|
nouveau_irq_register(dev, 25, nvc0_runk140_isr);
|
|
|
|
if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) ||
|
|
nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) ||
|
|
nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) ||
|
|
nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) {
|
|
ret = 0;
|
|
goto error;
|
|
}
|
|
|
|
|
|
ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
|
|
if (ret)
|
|
goto error;
|
|
|
|
ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
|
|
if (ret)
|
|
goto error;
|
|
|
|
for (i = 0; i < 0x1000; i += 4) {
|
|
nv_wo32(priv->unk4188b4, i, 0x00000010);
|
|
nv_wo32(priv->unk4188b8, i, 0x00000010);
|
|
}
|
|
|
|
priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f;
|
|
priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
|
|
for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
|
|
priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
|
|
priv->tp_total += priv->tp_nr[gpc];
|
|
}
|
|
|
|
/*XXX: these need figuring out... */
|
|
switch (dev_priv->chipset) {
|
|
case 0xc0:
|
|
if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
|
|
priv->magic_not_rop_nr = 0x07;
|
|
/* filled values up to tp_total, the rest 0 */
|
|
priv->magicgpc918 = 0x000ba2e9;
|
|
} else
|
|
if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
|
|
priv->magic_not_rop_nr = 0x05;
|
|
priv->magicgpc918 = 0x00092493;
|
|
} else
|
|
if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
|
|
priv->magic_not_rop_nr = 0x06;
|
|
priv->magicgpc918 = 0x00088889;
|
|
}
|
|
break;
|
|
case 0xc3: /* 450, 4/0/0/0, 2 */
|
|
priv->magic_not_rop_nr = 0x03;
|
|
priv->magicgpc918 = 0x00200000;
|
|
break;
|
|
case 0xc4: /* 460, 3/4/0/0, 4 */
|
|
priv->magic_not_rop_nr = 0x01;
|
|
priv->magicgpc918 = 0x00124925;
|
|
break;
|
|
}
|
|
|
|
if (!priv->magic_not_rop_nr) {
|
|
NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
|
|
priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
|
|
priv->tp_nr[3], priv->rop_nr);
|
|
/* use 0xc3's values... */
|
|
priv->magic_not_rop_nr = 0x03;
|
|
priv->magicgpc918 = 0x00200000;
|
|
}
|
|
|
|
NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
|
|
NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
|
|
NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
|
|
NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
|
|
NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
|
|
return 0;
|
|
|
|
error:
|
|
nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR);
|
|
return ret;
|
|
}
|
|
|
|
MODULE_FIRMWARE("nouveau/nvc0_fuc409c");
|
|
MODULE_FIRMWARE("nouveau/nvc0_fuc409d");
|
|
MODULE_FIRMWARE("nouveau/nvc0_fuc41ac");
|
|
MODULE_FIRMWARE("nouveau/nvc0_fuc41ad");
|
|
MODULE_FIRMWARE("nouveau/nvc3_fuc409c");
|
|
MODULE_FIRMWARE("nouveau/nvc3_fuc409d");
|
|
MODULE_FIRMWARE("nouveau/nvc3_fuc41ac");
|
|
MODULE_FIRMWARE("nouveau/nvc3_fuc41ad");
|
|
MODULE_FIRMWARE("nouveau/nvc4_fuc409c");
|
|
MODULE_FIRMWARE("nouveau/nvc4_fuc409d");
|
|
MODULE_FIRMWARE("nouveau/nvc4_fuc41ac");
|
|
MODULE_FIRMWARE("nouveau/nvc4_fuc41ad");
|
|
MODULE_FIRMWARE("nouveau/fuc409c");
|
|
MODULE_FIRMWARE("nouveau/fuc409d");
|
|
MODULE_FIRMWARE("nouveau/fuc41ac");
|
|
MODULE_FIRMWARE("nouveau/fuc41ad");
|