Felipe Balbi fae2b904aa usb: dwc3: workaround: U1/U2 -> U0 transiton ... RTL revisions <1.83a have an issue where, depending on the link partner, the USB link might do multiple entry/exit of low power states before a transfer takes place causing degraded throughput. The suggested workaround is to clear bits 12:9 of DCTL register if we see a transition from U1|U2 to U0 and only re-enable that on a transfer complete IRQ and we have no pending transfers on any of the enabled endpoints. Signed-off-by: Felipe Balbi <balbi@ti.com>		2011-12-12 11:48:34 +02:00
..
core.c	usb: dwc3: move generic dwc3 code from gadget into core	2011-12-12 11:48:27 +02:00
core.h	usb: dwc3: workaround: U1/U2 -> U0 transiton	2011-12-12 11:48:34 +02:00
debug.h	usb: dwc: remove "All rights reserved" statement.	2011-10-04 10:25:52 -07:00
debugfs.c	usb: dwc3: fix sparse errors	2011-12-12 11:48:29 +02:00
dwc3-omap.c	usb: dwc3: omap: add multiple instances support to OMAP	2011-12-12 11:48:23 +02:00
dwc3-pci.c	usb: dwc3: move dwc3 device ID bitmap to core.c	2011-12-12 11:48:21 +02:00
ep0.c	usb: dwc3: ep0: handle delayed_status again	2011-12-12 11:48:31 +02:00
gadget.c	usb: dwc3: workaround: U1/U2 -> U0 transiton	2011-12-12 11:48:34 +02:00
gadget.h	usb: dwc3: fix few coding style problems	2011-12-12 11:48:29 +02:00
host.c	usb: dwc3: host: remove unused includes	2011-12-12 11:48:19 +02:00
io.h	usb: dwc3: fix few coding style problems	2011-12-12 11:48:29 +02:00
Kconfig	usb: dwc3: depend on both Host and Gadget stacks	2011-12-12 11:48:14 +02:00
Makefile	usb: dwc3: always compile gadget side too	2011-12-12 11:48:13 +02:00