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b50f1704e9
This patch includes generic codes for memory management. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
50 lines
1.2 KiB
Text
50 lines
1.2 KiB
Text
comment "Processor Type"
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# Select CPU types depending on the architecture selected. This selects
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# which CPUs we support in the kernel image, and the compiler instruction
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# optimiser behaviour.
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config CPU_UCV2
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def_bool y
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comment "Processor Features"
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config CPU_ICACHE_DISABLE
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bool "Disable I-Cache (I-bit)"
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help
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Say Y here to disable the processor instruction cache. Unless
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you have a reason not to or are unsure, say N.
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config CPU_DCACHE_DISABLE
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bool "Disable D-Cache (D-bit)"
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help
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Say Y here to disable the processor data cache. Unless
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you have a reason not to or are unsure, say N.
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config CPU_DCACHE_WRITETHROUGH
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bool "Force write through D-cache"
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help
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Say Y here to use the data cache in writethrough mode. Unless you
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specifically require this or are unsure, say N.
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config CPU_DCACHE_LINE_DISABLE
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bool "Disable D-cache line ops"
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default y
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help
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Say Y here to disable the data cache line operations.
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config CPU_TLB_SINGLE_ENTRY_DISABLE
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bool "Disable TLB single entry ops"
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default y
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help
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Say Y here to disable the TLB single entry operations.
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config SWIOTLB
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def_bool y
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config IOMMU_HELPER
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def_bool SWIOTLB
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config NEED_SG_DMA_LENGTH
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def_bool SWIOTLB
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