mirror of
https://github.com/torvalds/linux
synced 2024-10-04 10:26:40 +00:00
4140d77a02
The IOMMU driver shares the pasid table for PCI alias devices. When the
RID2PASID entry of the shared pasid table has been filled by the first
device, the subsequent device will encounter the "DMAR: Setup RID2PASID
failed" failure as the pasid entry has already been marked as present.
As the result, the IOMMU probing process will be aborted.
On the contrary, when any alias device is hot-removed from the system,
for example, by writing to /sys/bus/pci/devices/.../remove, the shared
RID2PASID will be cleared without any notifications to other devices.
As the result, any DMAs from those rest devices are blocked.
Sharing pasid table among PCI alias devices could save two memory pages
for devices underneath the PCIe-to-PCI bridges. Anyway, considering that
those devices are rare on modern platforms that support VT-d in scalable
mode and the saved memory is negligible, it's reasonable to remove this
part of immature code to make the driver feasible and stable.
Fixes: ef848b7e5a ("iommu/vt-d: Setup pasid entry for RID2PASID support")
Reported-by: Chenyi Qiang <chenyi.qiang@intel.com>
Reported-by: Ethan Zhao <haifeng.zhao@linux.intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Ethan Zhao <haifeng.zhao@linux.intel.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220623065720.727849-1-baolu.lu@linux.intel.com
Link: https://lore.kernel.org/r/20220625133430.2200315-2-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
128 lines
3.8 KiB
C
128 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* pasid.h - PASID idr, table and entry header
|
|
*
|
|
* Copyright (C) 2018 Intel Corporation
|
|
*
|
|
* Author: Lu Baolu <baolu.lu@linux.intel.com>
|
|
*/
|
|
|
|
#ifndef __INTEL_PASID_H
|
|
#define __INTEL_PASID_H
|
|
|
|
#define PASID_RID2PASID 0x0
|
|
#define PASID_MIN 0x1
|
|
#define PASID_MAX 0x100000
|
|
#define PASID_PTE_MASK 0x3F
|
|
#define PASID_PTE_PRESENT 1
|
|
#define PASID_PTE_FPD 2
|
|
#define PDE_PFN_MASK PAGE_MASK
|
|
#define PASID_PDE_SHIFT 6
|
|
#define MAX_NR_PASID_BITS 20
|
|
#define PASID_TBL_ENTRIES BIT(PASID_PDE_SHIFT)
|
|
|
|
#define is_pasid_enabled(entry) (((entry)->lo >> 3) & 0x1)
|
|
#define get_pasid_dir_size(entry) (1 << ((((entry)->lo >> 9) & 0x7) + 7))
|
|
|
|
/* Virtual command interface for enlightened pasid management. */
|
|
#define VCMD_CMD_ALLOC 0x1
|
|
#define VCMD_CMD_FREE 0x2
|
|
#define VCMD_VRSP_IP 0x1
|
|
#define VCMD_VRSP_SC(e) (((e) & 0xff) >> 1)
|
|
#define VCMD_VRSP_SC_SUCCESS 0
|
|
#define VCMD_VRSP_SC_NO_PASID_AVAIL 16
|
|
#define VCMD_VRSP_SC_INVALID_PASID 16
|
|
#define VCMD_VRSP_RESULT_PASID(e) (((e) >> 16) & 0xfffff)
|
|
#define VCMD_CMD_OPERAND(e) ((e) << 16)
|
|
/*
|
|
* Domain ID reserved for pasid entries programmed for first-level
|
|
* only and pass-through transfer modes.
|
|
*/
|
|
#define FLPT_DEFAULT_DID 1
|
|
|
|
/*
|
|
* The SUPERVISOR_MODE flag indicates a first level translation which
|
|
* can be used for access to kernel addresses. It is valid only for
|
|
* access to the kernel's static 1:1 mapping of physical memory — not
|
|
* to vmalloc or even module mappings.
|
|
*/
|
|
#define PASID_FLAG_SUPERVISOR_MODE BIT(0)
|
|
#define PASID_FLAG_NESTED BIT(1)
|
|
#define PASID_FLAG_PAGE_SNOOP BIT(2)
|
|
|
|
/*
|
|
* The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first-
|
|
* level translation, otherwise, 4-level paging will be used.
|
|
*/
|
|
#define PASID_FLAG_FL5LP BIT(1)
|
|
|
|
struct pasid_dir_entry {
|
|
u64 val;
|
|
};
|
|
|
|
struct pasid_entry {
|
|
u64 val[8];
|
|
};
|
|
|
|
#define PASID_ENTRY_PGTT_FL_ONLY (1)
|
|
#define PASID_ENTRY_PGTT_SL_ONLY (2)
|
|
#define PASID_ENTRY_PGTT_NESTED (3)
|
|
#define PASID_ENTRY_PGTT_PT (4)
|
|
|
|
/* The representative of a PASID table */
|
|
struct pasid_table {
|
|
void *table; /* pasid table pointer */
|
|
int order; /* page order of pasid table */
|
|
u32 max_pasid; /* max pasid */
|
|
};
|
|
|
|
/* Get PRESENT bit of a PASID directory entry. */
|
|
static inline bool pasid_pde_is_present(struct pasid_dir_entry *pde)
|
|
{
|
|
return READ_ONCE(pde->val) & PASID_PTE_PRESENT;
|
|
}
|
|
|
|
/* Get PASID table from a PASID directory entry. */
|
|
static inline struct pasid_entry *
|
|
get_pasid_table_from_pde(struct pasid_dir_entry *pde)
|
|
{
|
|
if (!pasid_pde_is_present(pde))
|
|
return NULL;
|
|
|
|
return phys_to_virt(READ_ONCE(pde->val) & PDE_PFN_MASK);
|
|
}
|
|
|
|
/* Get PRESENT bit of a PASID table entry. */
|
|
static inline bool pasid_pte_is_present(struct pasid_entry *pte)
|
|
{
|
|
return READ_ONCE(pte->val[0]) & PASID_PTE_PRESENT;
|
|
}
|
|
|
|
/* Get PGTT field of a PASID table entry */
|
|
static inline u16 pasid_pte_get_pgtt(struct pasid_entry *pte)
|
|
{
|
|
return (u16)((READ_ONCE(pte->val[0]) >> 6) & 0x7);
|
|
}
|
|
|
|
extern unsigned int intel_pasid_max_id;
|
|
int intel_pasid_alloc_table(struct device *dev);
|
|
void intel_pasid_free_table(struct device *dev);
|
|
struct pasid_table *intel_pasid_get_table(struct device *dev);
|
|
int intel_pasid_setup_first_level(struct intel_iommu *iommu,
|
|
struct device *dev, pgd_t *pgd,
|
|
u32 pasid, u16 did, int flags);
|
|
int intel_pasid_setup_second_level(struct intel_iommu *iommu,
|
|
struct dmar_domain *domain,
|
|
struct device *dev, u32 pasid);
|
|
int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
|
|
struct dmar_domain *domain,
|
|
struct device *dev, u32 pasid);
|
|
void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
|
|
struct device *dev, u32 pasid,
|
|
bool fault_ignore);
|
|
int vcmd_alloc_pasid(struct intel_iommu *iommu, u32 *pasid);
|
|
void vcmd_free_pasid(struct intel_iommu *iommu, u32 pasid);
|
|
void intel_pasid_setup_page_snoop_control(struct intel_iommu *iommu,
|
|
struct device *dev, u32 pasid);
|
|
#endif /* __INTEL_PASID_H */
|