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f262f28c14
This patch adds a new class in devfreq, devfreq_event, which provides raw data (e.g., memory bus utilization, GPU utilization) for devfreq governors. - devfreq_event device : Provides raw data for a governor of a devfreq device - devfreq device : Monitors device state and changes frequency/voltage of the device using the raw data from its devfreq_event device. A devfreq device dertermines performance states (normally the frequency and the voltage vlues) based on the results its designtated devfreq governor: e.g., ondemand, performance, powersave. In order to give such results required by a devfreq device, the devfreq governor requires data that indicates the performance requirement given to the devfreq device. The conventional (previous) implementatino of devfreq subsystem requires a devfreq device driver to implement its own mechanism to acquire performance requirement for its governor. However, there had been issues with such requirements: 1. Although performance requirement of such devices is usually acquired from common devices (PMU/PPMU), we do not have any abstract structure to represent them properly. 2. Such performance requirement devices (PMU/PPMU) are actual hardware pieces that may be represented by Device Tree directly while devfreq device itself is a virtual entity that are not considered to be represented by Device Tree according to Device Tree folks. In order to address such issues, a devferq_event device (represented by this patch) provides a template for device drivers representing performance monitoring unit, which gives the basic or raw data for preformance requirement, which in turn, is required by devfreq governors. The following description explains the feature of two kind of devfreq class: - devfreq class (existing) : devfreq consumer device use raw data from devfreq_event device for determining proper current system state and change voltage/frequency dynamically using various governors. - devfreq_event class (new) : Provide measured raw data to devfreq device for governor Cc: MyungJoo Ham <myungjoo.ham@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [Commit message rewritten & conflict resolved by MyungJoo] Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
94 lines
2.3 KiB
C
94 lines
2.3 KiB
C
/*
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* exynos_ppmu.h - EXYNOS PPMU header file
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Author : Chanwoo Choi <cw00.choi@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __EXYNOS_PPMU_H__
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#define __EXYNOS_PPMU_H__
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enum ppmu_state {
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PPMU_DISABLE = 0,
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PPMU_ENABLE,
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};
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enum ppmu_counter {
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PPMU_PMNCNT0 = 0,
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PPMU_PMNCNT1,
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PPMU_PMNCNT2,
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PPMU_PMNCNT3,
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PPMU_PMNCNT_MAX,
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};
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enum ppmu_event_type {
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PPMU_RO_BUSY_CYCLE_CNT = 0x0,
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PPMU_WO_BUSY_CYCLE_CNT = 0x1,
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PPMU_RW_BUSY_CYCLE_CNT = 0x2,
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PPMU_RO_REQUEST_CNT = 0x3,
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PPMU_WO_REQUEST_CNT = 0x4,
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PPMU_RO_DATA_CNT = 0x5,
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PPMU_WO_DATA_CNT = 0x6,
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PPMU_RO_LATENCY = 0x12,
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PPMU_WO_LATENCY = 0x16,
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};
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enum ppmu_reg {
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/* PPC control register */
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PPMU_PMNC = 0x00,
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PPMU_CNTENS = 0x10,
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PPMU_CNTENC = 0x20,
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PPMU_INTENS = 0x30,
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PPMU_INTENC = 0x40,
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PPMU_FLAG = 0x50,
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/* Cycle Counter and Performance Event Counter Register */
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PPMU_CCNT = 0x100,
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PPMU_PMCNT0 = 0x110,
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PPMU_PMCNT1 = 0x120,
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PPMU_PMCNT2 = 0x130,
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PPMU_PMCNT3_HIGH = 0x140,
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PPMU_PMCNT3_LOW = 0x150,
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/* Bus Event Generator */
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PPMU_BEVT0SEL = 0x1000,
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PPMU_BEVT1SEL = 0x1100,
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PPMU_BEVT2SEL = 0x1200,
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PPMU_BEVT3SEL = 0x1300,
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PPMU_COUNTER_RESET = 0x1810,
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PPMU_READ_OVERFLOW_CNT = 0x1810,
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PPMU_READ_UNDERFLOW_CNT = 0x1814,
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PPMU_WRITE_OVERFLOW_CNT = 0x1850,
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PPMU_WRITE_UNDERFLOW_CNT = 0x1854,
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PPMU_READ_PENDING_CNT = 0x1880,
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PPMU_WRITE_PENDING_CNT = 0x1884
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};
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/* PMNC register */
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#define PPMU_PMNC_CC_RESET_SHIFT 2
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#define PPMU_PMNC_COUNTER_RESET_SHIFT 1
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#define PPMU_PMNC_ENABLE_SHIFT 0
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#define PPMU_PMNC_START_MODE_MASK BIT(16)
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#define PPMU_PMNC_CC_DIVIDER_MASK BIT(3)
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#define PPMU_PMNC_CC_RESET_MASK BIT(2)
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#define PPMU_PMNC_COUNTER_RESET_MASK BIT(1)
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#define PPMU_PMNC_ENABLE_MASK BIT(0)
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/* CNTENS/CNTENC/INTENS/INTENC/FLAG register */
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#define PPMU_CCNT_MASK BIT(31)
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#define PPMU_PMCNT3_MASK BIT(3)
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#define PPMU_PMCNT2_MASK BIT(2)
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#define PPMU_PMCNT1_MASK BIT(1)
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#define PPMU_PMCNT0_MASK BIT(0)
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/* PPMU_PMNCTx/PPMU_BETxSEL registers */
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#define PPMU_PMNCT(x) (PPMU_PMCNT0 + (0x10 * x))
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#define PPMU_BEVTxSEL(x) (PPMU_BEVT0SEL + (0x100 * x))
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#endif /* __EXYNOS_PPMU_H__ */
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