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f64603c972
For some reason the mod clock for the Allwinner F1C100s CIR (infrared receiver) peripheral was not modeled in the CCU driver. Add the clock description to the list, and wire it up in the clock list. By assigning a new clock ID at the end, it extends the number of clocks. This allows to use the CIR peripheral on any F1C100s series board. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-5-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
35 lines
747 B
C
35 lines
747 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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*/
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#ifndef _CCU_SUNIV_F1C100S_H_
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#define _CCU_SUNIV_F1C100S_H_
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#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
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#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
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#define CLK_PLL_CPU 0
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#define CLK_PLL_AUDIO_BASE 1
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#define CLK_PLL_AUDIO 2
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#define CLK_PLL_AUDIO_2X 3
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#define CLK_PLL_AUDIO_4X 4
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#define CLK_PLL_AUDIO_8X 5
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#define CLK_PLL_VIDEO 6
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#define CLK_PLL_VIDEO_2X 7
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#define CLK_PLL_VE 8
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#define CLK_PLL_DDR0 9
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#define CLK_PLL_PERIPH 10
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/* CPU clock is exported */
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#define CLK_AHB 12
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#define CLK_APB 13
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/* All bus gates, DRAM gates and mod clocks are exported */
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#define CLK_NUMBER (CLK_IR + 1)
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#endif /* _CCU_SUNIV_F1C100S_H_ */
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