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Chips such as e500mc that implement category E.HV in Power ISA 2.06 provide hardware virtualization features, including a new MSR mode for guest state. The guest OS can perform many operations without trapping into the hypervisor, including transitions to and from guest userspace. Since we can use SRR1[GS] to reliably tell whether an exception came from guest state, instead of messing around with IVPR, we use DO_KVM similarly to book3s. Current issues include: - Machine checks from guest state are not routed to the host handler. - The guest can cause a host oops by executing an emulated instruction in a page that lacks read permission. Existing e500/4xx support has the same problem. Includes work by Ashish Kalra <Ashish.Kalra@freescale.com>, Varun Sethi <Varun.Sethi@freescale.com>, and Liu Yu <yu.liu@freescale.com>. Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: remove pt_regs usage] Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
50 lines
1.5 KiB
C
50 lines
1.5 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*/
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#ifndef ASM_KVM_BOOKE_HV_ASM_H
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#define ASM_KVM_BOOKE_HV_ASM_H
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#ifdef __ASSEMBLY__
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/*
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* All exceptions from guest state must go through KVM
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* (except for those which are delivered directly to the guest) --
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* there are no exceptions for which we fall through directly to
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* the normal host handler.
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*
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* Expected inputs (normal exceptions):
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* SCRATCH0 = saved r10
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* r10 = thread struct
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* r11 = appropriate SRR1 variant (currently used as scratch)
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* r13 = saved CR
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* *(r10 + THREAD_NORMSAVE(0)) = saved r11
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* *(r10 + THREAD_NORMSAVE(2)) = saved r13
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*
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* Expected inputs (crit/mcheck/debug exceptions):
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* appropriate SCRATCH = saved r8
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* r8 = exception level stack frame
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* r9 = *(r8 + _CCR) = saved CR
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* r11 = appropriate SRR1 variant (currently used as scratch)
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* *(r8 + GPR9) = saved r9
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* *(r8 + GPR10) = saved r10 (r10 not yet clobbered)
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* *(r8 + GPR11) = saved r11
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*/
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.macro DO_KVM intno srr1
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#ifdef CONFIG_KVM_BOOKE_HV
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BEGIN_FTR_SECTION
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mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */
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bf 3, kvmppc_resume_\intno\()_\srr1
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b kvmppc_handler_\intno\()_\srr1
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kvmppc_resume_\intno\()_\srr1:
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END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
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#endif
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.endm
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#endif /*__ASSEMBLY__ */
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#endif /* ASM_KVM_BOOKE_HV_ASM_H */
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