Catalin Marinas 6ecba8eb51 arm64: Use bus notifiers to set per-device coherent DMA ops ... Recently, the default DMA ops have been changed to non-coherent for alignment with 32-bit ARM platforms (and DT files). This patch adds bus notifiers to be able to set the coherent DMA ops (with no cache maintenance) for devices explicitly marked as coherent via the "dma-coherent" DT property. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>		2014-05-03 22:20:34 +01:00
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cache.S	arm64: Fix DMA range invalidation for cache line unaligned buffers	2014-04-08 11:45:08 +01:00
context.c
copypage.c
dma-mapping.c	arm64: Use bus notifiers to set per-device coherent DMA ops	2014-05-03 22:20:34 +01:00
extable.c
fault.c	arm64: Make do_bad_area() function static	2013-09-20 09:56:05 +01:00
flush.c	arm64: Remove __flush_dcache_page()	2013-06-07 17:58:30 +01:00
hugetlbpage.c	mm: migrate: check movability of hugepage in unmap_and_move_huge_page()	2013-09-11 15:57:49 -07:00
init.c	Devicetree changes for v3.15	2014-04-02 14:27:15 -07:00
ioremap.c	arm64: add early_ioremap support	2014-04-07 16:36:15 -07:00
Makefile	ARM64: mm: HugeTLB support.	2013-06-14 09:52:40 +01:00
mm.h	arm64: Remove __flush_dcache_page()	2013-06-07 17:58:30 +01:00
mmap.c	mm: remove free_area_cache	2013-07-10 18:11:34 -07:00
mmu.c	arm64: Fix for the arm64 kern_addr_valid() function	2014-05-03 22:20:29 +01:00
pgd.c	arm64: simplify pgd_alloc	2014-02-05 10:45:07 +00:00
proc-macros.S	arm64: mm: use ubfm for dcache_line_size	2014-01-22 16:23:58 +00:00
proc.S	arm64: Update the TCR_EL1 translation granule definitions for 16K pages	2014-04-03 10:43:11 +01:00
tlb.S	arm64: use correct register width when retrieving ASID	2013-09-25 16:42:23 +01:00