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f0bd6881e8
Instead of relying on the bootloader for configuring the FEC pins, pass the FEC pin configuration via device tree instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
69 lines
1.5 KiB
Plaintext
69 lines
1.5 KiB
Plaintext
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx25.dtsi"
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/ {
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model = "Freescale i.MX25 Product Development Kit";
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compatible = "fsl,imx25-pdk", "fsl,imx25";
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memory {
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reg = <0x80000000 0x4000000>;
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};
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};
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&fec {
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phy-mode = "rmii";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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status = "okay";
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};
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&iomuxc {
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imx25-pdk {
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
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MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
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MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
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MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
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MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
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MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
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MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
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MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
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MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX25_PAD_UART1_RTS__UART1_RTS 0xe0
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MX25_PAD_UART1_CTS__UART1_CTS 0xe0
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MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
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MX25_PAD_UART1_RXD__UART1_RXD 0xc0
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>;
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};
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};
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};
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&nfc {
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nand-on-flash-bbt;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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fsl,uart-has-rtscts;
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status = "okay";
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};
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