linux/include/asm-arm/arch-ixp4xx/irqs.h
Rod Whitby 3145d8a6cc [ARM] 3215/1: Iomega NAS 100d (MACH_NAS100D) machine support
Patch from Rod Whitby

This patch adds support for a new arm/ixp4xx machine - the Iomega NAS 100d network attached storage product.  The NAS100D is a consumer device containing a 266MHz Intel IXP420 processor, 16MB of flash, 64MB of RAM, a 160Gb internal IDE hard disk, and 802.11b/g wireless on an Atheros mini-PCI card.

Work on porting the latest 2.6.x kernel to this device is being done by
the NSLU2-Linux project (the same team who maintains the port to the
Linksys NSLU2 device).  In particular, the majority of this patch was
authored by Alessandro Zummo, based on the work done for MACH_NSLU2
support by the NSLU2-Linux core team of developers.

MACH_NAS100D (as implemented by this patch) can be enabled in jumbo
ixp4xx kernels without any affect on the other machines supported by
that kernel.

This patch applies cleanly against 2.6.15-rc7 and should be trivial to
apply to later kernel versions. It does not depend upon any other
patches.

Modified files (and number of lines inserted):
 arch/arm/mach-ixp4xx/Kconfig           |    8
 arch/arm/mach-ixp4xx/Makefile          |    1
 include/asm-arm/arch-ixp4xx/hardware.h |    1
 include/asm-arm/arch-ixp4xx/irqs.h     |    9
 include/asm-arm/arch-ixp4xx/nas100d.h  |   75
 arch/arm/mach-ixp4xx/nas100d-pci.c     |   77
 arch/arm/mach-ixp4xx/nas100d-power.c   |   69
 arch/arm/mach-ixp4xx/nas100d-setup.c   |  133

-- Rod Whitby (NSLU2-Linux project lead)

Signed-off-by: Rod Whitby <rod@whitby.id.au>
Signed-off-by: Alessandro Zummo <a.zummo@towertech.it>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-04 17:17:11 +00:00

113 lines
2.9 KiB
C

/*
* include/asm-arm/arch-ixp4xx/irqs.h
*
* IRQ definitions for IXP4XX based systems
*
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _ARCH_IXP4XX_IRQS_H_
#define _ARCH_IXP4XX_IRQS_H_
#define IRQ_IXP4XX_NPEA 0
#define IRQ_IXP4XX_NPEB 1
#define IRQ_IXP4XX_NPEC 2
#define IRQ_IXP4XX_QM1 3
#define IRQ_IXP4XX_QM2 4
#define IRQ_IXP4XX_TIMER1 5
#define IRQ_IXP4XX_GPIO0 6
#define IRQ_IXP4XX_GPIO1 7
#define IRQ_IXP4XX_PCI_INT 8
#define IRQ_IXP4XX_PCI_DMA1 9
#define IRQ_IXP4XX_PCI_DMA2 10
#define IRQ_IXP4XX_TIMER2 11
#define IRQ_IXP4XX_USB 12
#define IRQ_IXP4XX_UART2 13
#define IRQ_IXP4XX_TIMESTAMP 14
#define IRQ_IXP4XX_UART1 15
#define IRQ_IXP4XX_WDOG 16
#define IRQ_IXP4XX_AHB_PMU 17
#define IRQ_IXP4XX_XSCALE_PMU 18
#define IRQ_IXP4XX_GPIO2 19
#define IRQ_IXP4XX_GPIO3 20
#define IRQ_IXP4XX_GPIO4 21
#define IRQ_IXP4XX_GPIO5 22
#define IRQ_IXP4XX_GPIO6 23
#define IRQ_IXP4XX_GPIO7 24
#define IRQ_IXP4XX_GPIO8 25
#define IRQ_IXP4XX_GPIO9 26
#define IRQ_IXP4XX_GPIO10 27
#define IRQ_IXP4XX_GPIO11 28
#define IRQ_IXP4XX_GPIO12 29
#define IRQ_IXP4XX_SW_INT1 30
#define IRQ_IXP4XX_SW_INT2 31
#define IRQ_IXP4XX_USB_HOST 32
#define IRQ_IXP4XX_I2C 33
#define IRQ_IXP4XX_SSP 34
#define IRQ_IXP4XX_TSYNC 35
#define IRQ_IXP4XX_EAU_DONE 36
#define IRQ_IXP4XX_SHA_DONE 37
#define IRQ_IXP4XX_SWCP_PE 58
#define IRQ_IXP4XX_QM_PE 60
#define IRQ_IXP4XX_MCU_ECC 61
#define IRQ_IXP4XX_EXP_PE 62
/*
* Only first 32 sources are valid if running on IXP42x systems
*/
#ifndef CONFIG_CPU_IXP46X
#define NR_IRQS 32
#else
#define NR_IRQS 64
#endif
#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)
/*
* IXDP425 board IRQs
*/
#define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11
#define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10
#define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9
#define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8
/*
* PrPMC1100 Board IRQs
*/
#define IRQ_PRPMC1100_PCI_INTA IRQ_IXP4XX_GPIO11
#define IRQ_PRPMC1100_PCI_INTB IRQ_IXP4XX_GPIO10
#define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9
#define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8
/*
* ADI Coyote Board IRQs
*/
#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6
#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11
#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
/*
* NSLU2 board IRQs
*/
#define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11
#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10
#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9
/*
* NAS100D board IRQs
*/
#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11
#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10
#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9
#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8
#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7
#endif