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https://github.com/torvalds/linux
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efe90d273b
Don't set HWCAP_VFP in the processor support file; not only does it depend on the processor features, but it also depends on the support code being present. Therefore, only set it if the support code detects that we have a VFP coprocessor attached. Also, move the VFP handling of the coprocessor access register into the VFP support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
278 lines
6.5 KiB
ArmAsm
278 lines
6.5 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-v6.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Modified by Catalin Marinas for noMMU support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the ARMv6 processor support.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/elf.h>
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#include <asm/hardware/arm_scu.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include "proc-macros.S"
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#define D_CACHE_LINE_SIZE 32
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#define TTB_C (1 << 0)
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#define TTB_S (1 << 1)
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#define TTB_IMP (1 << 2)
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#define TTB_RGN_NC (0 << 3)
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#define TTB_RGN_WBWA (1 << 3)
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#define TTB_RGN_WT (2 << 3)
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#define TTB_RGN_WB (3 << 3)
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ENTRY(cpu_v6_proc_init)
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mov pc, lr
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ENTRY(cpu_v6_proc_fin)
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stmfd sp!, {lr}
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cpsid if @ disable interrupts
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bl v6_flush_kern_cache_all
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x0006 @ .............ca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ldmfd sp!, {pc}
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/*
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* cpu_v6_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* - loc - location to jump to for soft reset
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*
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* It is assumed that:
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*/
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.align 5
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ENTRY(cpu_v6_reset)
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mov pc, r0
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/*
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* cpu_v6_do_idle()
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*
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* Idle the processor (eg, wait for interrupt).
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*
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* IRQs are already disabled.
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*/
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ENTRY(cpu_v6_do_idle)
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mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
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mov pc, lr
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ENTRY(cpu_v6_dcache_clean_area)
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#ifndef TLB_CAN_READ_FROM_L1_CACHE
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #D_CACHE_LINE_SIZE
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subs r1, r1, #D_CACHE_LINE_SIZE
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bhi 1b
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#endif
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mov pc, lr
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/*
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* cpu_arm926_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys
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*
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* - pgd_phys - physical address of new TTB
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*
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* It is assumed that:
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* - we are not using split page tables
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*/
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ENTRY(cpu_v6_switch_mm)
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#ifdef CONFIG_MMU
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mov r2, #0
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ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
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#ifdef CONFIG_SMP
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orr r0, r0, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
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#endif
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mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
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mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
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mcr p15, 0, r1, c13, c0, 1 @ set context ID
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#endif
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mov pc, lr
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/*
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* cpu_v6_set_pte(ptep, pte)
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*
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* Set a level 2 translation table entry.
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*
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* - ptep - pointer to level 2 translation table entry
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* (hardware version is stored at -1024 bytes)
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* - pte - PTE value to store
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*
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* Permissions:
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* YUWD APX AP1 AP0 SVC User
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* 0xxx 0 0 0 no acc no acc
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* 100x 1 0 1 r/o no acc
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* 10x0 1 0 1 r/o no acc
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* 1011 0 0 1 r/w no acc
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* 110x 0 1 0 r/w r/o
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* 11x0 0 1 0 r/w r/o
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* 1111 0 1 1 r/w r/w
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*/
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ENTRY(cpu_v6_set_pte)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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bic r2, r1, #0x000003f0
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bic r2, r2, #0x00000003
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orr r2, r2, #PTE_EXT_AP0 | 2
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tst r1, #L_PTE_WRITE
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tstne r1, #L_PTE_DIRTY
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orreq r2, r2, #PTE_EXT_APX
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tst r1, #L_PTE_USER
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orrne r2, r2, #PTE_EXT_AP1
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tstne r2, #PTE_EXT_APX
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bicne r2, r2, #PTE_EXT_APX | PTE_EXT_AP0
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tst r1, #L_PTE_YOUNG
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biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK
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tst r1, #L_PTE_EXEC
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orreq r2, r2, #PTE_EXT_XN
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tst r1, #L_PTE_PRESENT
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moveq r2, #0
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str r2, [r0]
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mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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#endif
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mov pc, lr
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cpu_v6_name:
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.asciz "Some Random V6 Processor"
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.align
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.section ".text.init", #alloc, #execinstr
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/*
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* __v6_setup
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*
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* Initialise TLB, Caches, and MMU state ready to switch the MMU
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* on. Return in r0 the new CP15 C1 control register setting.
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*
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* We automatically detect if we have a Harvard cache, and use the
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* Harvard cache control instructions insead of the unified cache
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* control instructions.
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*
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* This should be able to cover all ARMv6 cores.
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*
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* It is assumed that:
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* - cache type register is implemented
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*/
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__v6_setup:
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#ifdef CONFIG_SMP
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/* Set up the SCU on core 0 only */
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mrc p15, 0, r0, c0, c0, 5 @ CPU core number
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ands r0, r0, #15
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moveq r0, #0x10000000 @ SCU_BASE
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orreq r0, r0, #0x00100000
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ldreq r5, [r0, #SCU_CTRL]
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orreq r5, r5, #1
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streq r5, [r0, #SCU_CTRL]
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
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orr r0, r0, #0x20
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mcr p15, 0, r0, c1, c0, 1
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#endif
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#endif
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mov r0, #0
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mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r0, c2, c0, 2 @ TTB control register
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#ifdef CONFIG_SMP
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orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
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#endif
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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#endif /* CONFIG_MMU */
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adr r5, v6_crval
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ldmia r5, {r5, r6}
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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bic r0, r0, r5 @ clear bits them
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orr r0, r0, r6 @ set them
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mov pc, lr @ return to head.S:__ret
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/*
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* V X F I D LR
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* .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
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* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
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* 0 110 0011 1.00 .111 1101 < we want
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*/
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.type v6_crval, #object
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v6_crval:
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crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
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.type v6_processor_functions, #object
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ENTRY(v6_processor_functions)
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.word v6_early_abort
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.word cpu_v6_proc_init
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.word cpu_v6_proc_fin
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.word cpu_v6_reset
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.word cpu_v6_do_idle
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.word cpu_v6_dcache_clean_area
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.word cpu_v6_switch_mm
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.word cpu_v6_set_pte
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.size v6_processor_functions, . - v6_processor_functions
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.type cpu_arch_name, #object
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cpu_arch_name:
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.asciz "armv6"
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.size cpu_arch_name, . - cpu_arch_name
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.type cpu_elf_name, #object
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cpu_elf_name:
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.asciz "v6"
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.size cpu_elf_name, . - cpu_elf_name
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.align
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.section ".proc.info.init", #alloc, #execinstr
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/*
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* Match any ARMv6 processor core.
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*/
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.type __v6_proc_info, #object
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__v6_proc_info:
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.long 0x0007b000
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.long 0x0007f000
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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.long PMD_TYPE_SECT | \
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PMD_SECT_XN | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __v6_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
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.long cpu_v6_name
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.long v6_processor_functions
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.long v6wbi_tlb_fns
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.long v6_user_fns
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.long v6_cache_fns
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.size __v6_proc_info, . - __v6_proc_info
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