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The SRAM PA addresses are locally defined and used at different places, i.e. SRAM management code and idle sleep code. The macros are now defined at a centralized place, for easier maintenance. Tested on N900 and Beagleboard with full RET and OFF modes, using cpuidle and suspend. Signed-off-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon<nm@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
77 lines
1.9 KiB
C
77 lines
1.9 KiB
C
#ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
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#define __ARCH_ARM_MACH_OMAP2_SDRC_H
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/*
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* OMAP2 SDRC register definitions
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Copyright (C) 2007 Nokia Corporation
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*
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* Written by Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <plat/sdrc.h>
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#ifndef __ASSEMBLER__
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#include <linux/io.h>
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extern void __iomem *omap2_sdrc_base;
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extern void __iomem *omap2_sms_base;
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#define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg))
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#define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg))
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/* SDRC global register get/set */
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static inline void sdrc_write_reg(u32 val, u16 reg)
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{
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__raw_writel(val, OMAP_SDRC_REGADDR(reg));
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}
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static inline u32 sdrc_read_reg(u16 reg)
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{
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return __raw_readl(OMAP_SDRC_REGADDR(reg));
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}
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/* SMS global register get/set */
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static inline void sms_write_reg(u32 val, u16 reg)
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{
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__raw_writel(val, OMAP_SMS_REGADDR(reg));
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}
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static inline u32 sms_read_reg(u16 reg)
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{
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return __raw_readl(OMAP_SMS_REGADDR(reg));
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}
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#else
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#define OMAP242X_SDRC_REGADDR(reg) \
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OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
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#define OMAP243X_SDRC_REGADDR(reg) \
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OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
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#define OMAP34XX_SDRC_REGADDR(reg) \
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OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
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#endif /* __ASSEMBLER__ */
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/* Minimum frequency that the SDRC DLL can lock at */
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#define MIN_SDRC_DLL_LOCK_FREQ 83000000
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/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
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#define SDRC_MPURATE_SCALE 8
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/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
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#define SDRC_MPURATE_BASE_SHIFT 9
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/*
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* SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
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* 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
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*/
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#define SDRC_MPURATE_LOOPS 96
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#endif
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