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d1fd4fb69e
This code changes the detection procedure of i7core_edac. Instead of directly probing for MC registers, it probes for another register found on Nehalem. If found, it tries to pick the first MC PCI BUS. This should work fine with Xeon 35xx, but, on Xeon 55xx, this is at bus 254 and 255 that are not properly detected by the non-legacy PCI methods. The new detection code scans specifically at buses 254 and 255 for the Xeon 55xx devices. This code has not tested yet. After working, a change at the code will be needed, since the i7core is not yet ready for working with 2 sets of MC. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> |
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| blackfin | ||
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| m32r | ||
| m68k | ||
| m68knommu | ||
| microblaze | ||
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| score | ||
| sh | ||
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| x86 | ||
| xtensa | ||
| .gitignore | ||
| Kconfig | ||