linux/arch/riscv
Linus Torvalds 56d428ae1c RISC-V Patches for the 6.7 Merge Window, Part 2
* Support for handling misaligned accesses in S-mode.
 * Probing for misaligned access support is now properly cached and
   handled in parallel.
 * PTDUMP now reflects the SW reserved bits, as well as the PBMT and
   NAPOT extensions.
 * Performance improvements for TLB flushing.
 * Support for many new relocations in the module loader.
 * Various bug fixes and cleanups.
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Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull more RISC-V updates from Palmer Dabbelt:

 - Support for handling misaligned accesses in S-mode

 - Probing for misaligned access support is now properly cached and
   handled in parallel

 - PTDUMP now reflects the SW reserved bits, as well as the PBMT and
   NAPOT extensions

 - Performance improvements for TLB flushing

 - Support for many new relocations in the module loader

 - Various bug fixes and cleanups

* tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (51 commits)
  riscv: Optimize bitops with Zbb extension
  riscv: Rearrange hwcap.h and cpufeature.h
  drivers: perf: Do not broadcast to other cpus when starting a counter
  drivers: perf: Check find_first_bit() return value
  of: property: Add fw_devlink support for msi-parent
  RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
  riscv: Fix set_memory_XX() and set_direct_map_XX() by splitting huge linear mappings
  riscv: Don't use PGD entries for the linear mapping
  RISC-V: Probe misaligned access speed in parallel
  RISC-V: Remove __init on unaligned_emulation_finish()
  RISC-V: Show accurate per-hart isa in /proc/cpuinfo
  RISC-V: Don't rely on positional structure initialization
  riscv: Add tests for riscv module loading
  riscv: Add remaining module relocations
  riscv: Avoid unaligned access when relocating modules
  riscv: split cache ops out of dma-noncoherent.c
  riscv: Improve flush_tlb_kernel_range()
  riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb
  riscv: Improve flush_tlb_range() for hugetlb pages
  riscv: Improve tlb_flush()
  ...
2023-11-10 09:23:17 -08:00
..
boot RISC-V Patches for the 6.7 Merge Window, Part 2 2023-11-10 09:23:17 -08:00
configs RISC-V Patches for the 6.7 Merge Window, Part 2 2023-11-10 09:23:17 -08:00
errata riscv: errata: andes: Makefile: Fix randconfig build issue 2023-09-27 07:02:48 -07:00
include RISC-V Patches for the 6.7 Merge Window, Part 2 2023-11-10 09:23:17 -08:00
kernel RISC-V Patches for the 6.7 Merge Window, Part 2 2023-11-10 09:23:17 -08:00
kvm RISC-V Patches for the 6.7 Merge Window, Part 2 2023-11-10 09:23:17 -08:00
lib riscv: Use SYM_*() assembly macros instead of deprecated ones 2023-11-06 09:42:47 -08:00
mm RISC-V Patches for the 6.7 Merge Window, Part 2 2023-11-10 09:23:17 -08:00
net riscv, bpf: Track both a0 (RISC-V ABI) and a5 (BPF) return values 2023-10-09 15:21:25 +02:00
purgatory riscv: Use SYM_*() assembly macros instead of deprecated ones 2023-11-06 09:42:47 -08:00
tools riscv: Check relocations at compile time 2023-04-19 07:46:32 -07:00
Kbuild kexec: rename ARCH_HAS_KEXEC_PURGATORY 2023-08-18 10:18:54 -07:00
Kconfig RISC-V Patches for the 6.7 Merge Window, Part 2 2023-11-10 09:23:17 -08:00
Kconfig.debug riscv: Add tests for riscv module loading 2023-11-07 14:59:32 -08:00
Kconfig.errata riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT 2023-10-26 09:42:38 +02:00
Kconfig.socs SoC driver updates for 6.7 2023-11-01 14:46:51 -10:00
Makefile Merge patch "drivers: perf: Do not broadcast to other cpus when starting a counter" 2023-11-09 06:44:13 -08:00
Makefile.postlink kbuild: remove ARCH_POSTLINK from module builds 2023-10-28 21:10:08 +09:00