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41155b6f6d
Update the device-tree clock, memory, power and reset headers for Tegra234 by adding the definitions for all the various devices. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
40 lines
1.4 KiB
C
40 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
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#ifndef __ABI_MACH_T234_POWERGATE_T234_H_
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#define __ABI_MACH_T234_POWERGATE_T234_H_
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#define TEGRA234_POWER_DOMAIN_OFA 1U
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#define TEGRA234_POWER_DOMAIN_AUD 2U
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#define TEGRA234_POWER_DOMAIN_DISP 3U
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#define TEGRA234_POWER_DOMAIN_PCIEX8A 5U
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#define TEGRA234_POWER_DOMAIN_PCIEX4A 6U
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#define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U
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#define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U
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#define TEGRA234_POWER_DOMAIN_PCIEX1A 9U
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#define TEGRA234_POWER_DOMAIN_XUSBA 10U
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#define TEGRA234_POWER_DOMAIN_XUSBB 11U
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#define TEGRA234_POWER_DOMAIN_XUSBC 12U
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#define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U
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#define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U
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#define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U
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#define TEGRA234_POWER_DOMAIN_PCIEX8B 16U
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#define TEGRA234_POWER_DOMAIN_MGBEA 17U
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#define TEGRA234_POWER_DOMAIN_MGBEB 18U
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#define TEGRA234_POWER_DOMAIN_MGBEC 19U
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#define TEGRA234_POWER_DOMAIN_MGBED 20U
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#define TEGRA234_POWER_DOMAIN_ISPA 22U
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#define TEGRA234_POWER_DOMAIN_NVDEC 23U
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#define TEGRA234_POWER_DOMAIN_NVJPGA 24U
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#define TEGRA234_POWER_DOMAIN_NVENC 25U
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#define TEGRA234_POWER_DOMAIN_VI 28U
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#define TEGRA234_POWER_DOMAIN_VIC 29U
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#define TEGRA234_POWER_DOMAIN_PVA 30U
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#define TEGRA234_POWER_DOMAIN_DLAA 32U
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#define TEGRA234_POWER_DOMAIN_DLAB 33U
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#define TEGRA234_POWER_DOMAIN_CV 34U
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#define TEGRA234_POWER_DOMAIN_GPU 35U
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#define TEGRA234_POWER_DOMAIN_NVJPGB 36U
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#endif
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