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This is the framework for using XIVE in a PowerVM guest. The support is very similar to the native one in a much simpler form. Each source is associated with an Event State Buffer (ESB). This is a two bit state machine which is used to trigger events. The bits are named "P" (pending) and "Q" (queued) and can be controlled by MMIO. The Guest OS registers event (or notifications) queues on which the HW will post event data for a target to notify. Instead of OPAL calls, a set of Hypervisors call are used to configure the interrupt sources and the event/notification queues of the guest: - H_INT_GET_SOURCE_INFO used to obtain the address of the MMIO page of the Event State Buffer (PQ bits) entry associated with the source. - H_INT_SET_SOURCE_CONFIG assigns a source to a "target". - H_INT_GET_SOURCE_CONFIG determines to which "target" and "priority" is assigned to a source - H_INT_GET_QUEUE_INFO returns the address of the notification management page associated with the specified "target" and "priority". - H_INT_SET_QUEUE_CONFIG sets or resets the event queue for a given "target" and "priority". It is also used to set the notification config associated with the queue, only unconditional notification for the moment. Reset is performed with a queue size of 0 and queueing is disabled in that case. - H_INT_GET_QUEUE_CONFIG returns the queue settings for a given "target" and "priority". - H_INT_RESET resets all of the partition's interrupt exploitation structures to their initial state, losing all configuration set via the hcalls H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. - H_INT_SYNC issue a synchronisation on a source to make sure sure all notifications have reached their queue. As for XICS, the XIVE interface for the guest is described in the device tree under the "interrupt-controller" node. A couple of new properties are specific to XIVE : - "reg" contains the base address and size of the thread interrupt managnement areas (TIMA), also called rings, for the User level and for the Guest OS level. Only the Guest OS level is taken into account today. - "ibm,xive-eq-sizes" the size of the event queues. One cell per size supported, contains log2 of size, in ascending order. - "ibm,xive-lisn-ranges" the interrupt numbers ranges assigned to the guest. These are allocated using a simple bitmap. and also : - "/ibm,plat-res-int-priorities" contains a list of priorities that the hypervisor has reserved for its own use. Tested with a QEMU XIVE model for pseries and with the Power hypervisor. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> |
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| .. | ||
| ge | ||
| xics | ||
| xive | ||
| 6xx-suspend.S | ||
| axonram.c | ||
| cpm1.c | ||
| cpm2.c | ||
| cpm2_pic.c | ||
| cpm2_pic.h | ||
| cpm_common.c | ||
| dart.h | ||
| dart_iommu.c | ||
| dcr-low.S | ||
| dcr.c | ||
| ehv_pic.c | ||
| fsl_85xx_cache_ctlr.h | ||
| fsl_85xx_cache_sram.c | ||
| fsl_85xx_l2ctlr.c | ||
| fsl_gtm.c | ||
| fsl_lbc.c | ||
| fsl_mpic_err.c | ||
| fsl_mpic_timer_wakeup.c | ||
| fsl_msi.c | ||
| fsl_msi.h | ||
| fsl_pci.c | ||
| fsl_pci.h | ||
| fsl_pmc.c | ||
| fsl_rcpm.c | ||
| fsl_rio.c | ||
| fsl_rio.h | ||
| fsl_rmu.c | ||
| fsl_soc.c | ||
| fsl_soc.h | ||
| grackle.c | ||
| i8259.c | ||
| indirect_pci.c | ||
| ipic.c | ||
| ipic.h | ||
| Kconfig | ||
| Makefile | ||
| micropatch.c | ||
| mmio_nvram.c | ||
| mpc5xxx_clocks.c | ||
| mpic.c | ||
| mpic.h | ||
| mpic_msgr.c | ||
| mpic_msi.c | ||
| mpic_timer.c | ||
| mpic_u3msi.c | ||
| msi_bitmap.c | ||
| mv64x60.h | ||
| mv64x60_dev.c | ||
| mv64x60_pci.c | ||
| mv64x60_pic.c | ||
| mv64x60_udbg.c | ||
| of_rtc.c | ||
| pmi.c | ||
| rtc_cmos_setup.c | ||
| scom.c | ||
| simple_gpio.c | ||
| simple_gpio.h | ||
| tsi108_dev.c | ||
| tsi108_pci.c | ||
| udbg_memcons.c | ||
| xilinx_intc.c | ||
| xilinx_pci.c | ||