Max Filippov eab5e7a79d xtensa: initialize CPENABLE SR when core has one ... XCHAL_CP_NUM is defined in variant/tie.h and it is not included by head.S, leaving CPENABLE register uninitialised. XCHAL_HAVE_CP is defined in variant/core.h to 1 when core has CPENABLE SR. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>		2012-12-18 21:10:25 -08:00
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boot	xtensa: add XTFPGA DTS	2012-12-18 21:10:24 -08:00
configs	xtensa: drop CONFIG_EMBEDDED_RAMDISK	2012-10-03 15:13:09 -07:00
include	xtensa: add device trees support	2012-12-18 21:10:23 -08:00
kernel	xtensa: initialize CPENABLE SR when core has one	2012-12-18 21:10:25 -08:00
lib	xtensa: provide proper assembler function boundaries with ENDPROC()	2012-12-18 21:10:20 -08:00
mm	xtensa: fix build warning for arch/xtensa/mm/tlb.c	2012-12-18 21:10:21 -08:00
platforms	Use for_each_compatible_node() macro.	2012-12-18 21:10:25 -08:00
variants	xtensa: unbalanced parentheses	2012-12-18 21:10:20 -08:00
Kconfig	xtensa: add support for the XTFPGA boards	2012-12-18 21:10:24 -08:00
Kconfig.debug	xtensa: add s32c1i sanity check	2012-12-18 21:10:22 -08:00
Makefile	xtensa: add support for the XTFPGA boards	2012-12-18 21:10:24 -08:00