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https://github.com/torvalds/linux
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25498e5b3d
* 'next/driver' of git://git.linaro.org/people/arnd/arm-soc: hw_random: add driver for atmel true hardware random number generator ARM: at91: at91sam9g45: add trng clock and platform device MX53 Enable the AHCI SATA on MX53 SMD board MX53 Enable the AHCI SATA on MX53 LOCO board MX53 Enable the AHCI SATA on MX53 ARD board AHCI Add the AHCI SATA feature on the MX53 platforms Fix pata imx resource ARM: imx: Define functions for registering PATA ARM: imx: Add PATA clock support ARM: imx: Add PATA resources for other i.MX processors imx: efika: Enable pata. imx51: add pata clock imx51: add pata device Fix up trivial conflict (new selects next to each other from separate branches for EFIKA_COMMON) in arch/arm/mach-mx5/Kconfig
633 lines
15 KiB
C
633 lines
15 KiB
C
/*
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* based on code from the following
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* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
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* Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/gpio.h>
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#include <linux/leds.h>
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#include <linux/input.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/spi/flash.h>
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#include <linux/spi/spi.h>
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#include <linux/mfd/mc13892.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/consumer.h>
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#include <mach/common.h>
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#include <mach/hardware.h>
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#include <mach/iomux-mx51.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/ulpi.h>
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#include <mach/ulpi.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include "devices-imx51.h"
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#include "efika.h"
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#include "cpu_op-mx51.h"
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#define MX51_USB_CTRL_1_OFFSET 0x10
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#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
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#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
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#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
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#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
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#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
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#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
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#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
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static iomux_v3_cfg_t mx51efika_pads[] = {
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/* UART1 */
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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MX51_PAD_UART1_RTS__UART1_RTS,
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MX51_PAD_UART1_CTS__UART1_CTS,
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/* SD 1 */
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MX51_PAD_SD1_CMD__SD1_CMD,
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MX51_PAD_SD1_CLK__SD1_CLK,
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MX51_PAD_SD1_DATA0__SD1_DATA0,
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MX51_PAD_SD1_DATA1__SD1_DATA1,
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MX51_PAD_SD1_DATA2__SD1_DATA2,
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MX51_PAD_SD1_DATA3__SD1_DATA3,
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/* SD 2 */
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MX51_PAD_SD2_CMD__SD2_CMD,
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MX51_PAD_SD2_CLK__SD2_CLK,
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MX51_PAD_SD2_DATA0__SD2_DATA0,
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MX51_PAD_SD2_DATA1__SD2_DATA1,
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MX51_PAD_SD2_DATA2__SD2_DATA2,
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MX51_PAD_SD2_DATA3__SD2_DATA3,
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/* SD/MMC WP/CD */
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MX51_PAD_GPIO1_0__SD1_CD,
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MX51_PAD_GPIO1_1__SD1_WP,
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MX51_PAD_GPIO1_7__SD2_WP,
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MX51_PAD_GPIO1_8__SD2_CD,
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/* spi */
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MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
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MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
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MX51_PAD_CSPI1_SS0__GPIO4_24,
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MX51_PAD_CSPI1_SS1__GPIO4_25,
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MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
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MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
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MX51_PAD_GPIO1_6__GPIO1_6,
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/* USB HOST1 */
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MX51_PAD_USBH1_CLK__USBH1_CLK,
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MX51_PAD_USBH1_DIR__USBH1_DIR,
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MX51_PAD_USBH1_NXT__USBH1_NXT,
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MX51_PAD_USBH1_DATA0__USBH1_DATA0,
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MX51_PAD_USBH1_DATA1__USBH1_DATA1,
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MX51_PAD_USBH1_DATA2__USBH1_DATA2,
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MX51_PAD_USBH1_DATA3__USBH1_DATA3,
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MX51_PAD_USBH1_DATA4__USBH1_DATA4,
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MX51_PAD_USBH1_DATA5__USBH1_DATA5,
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MX51_PAD_USBH1_DATA6__USBH1_DATA6,
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MX51_PAD_USBH1_DATA7__USBH1_DATA7,
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/* USB HUB RESET */
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MX51_PAD_GPIO1_5__GPIO1_5,
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/* WLAN */
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MX51_PAD_EIM_A22__GPIO2_16,
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MX51_PAD_EIM_A16__GPIO2_10,
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/* USB PHY RESET */
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MX51_PAD_EIM_D27__GPIO2_9,
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};
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/* Serial ports */
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static const struct imxuart_platform_data uart_pdata = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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/* This function is board specific as the bit mask for the plldiv will also
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* be different for other Freescale SoCs, thus a common bitmask is not
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* possible and cannot get place in /plat-mxc/ehci.c.
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*/
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static int initialize_otg_port(struct platform_device *pdev)
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{
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u32 v;
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void __iomem *usb_base;
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void __iomem *usbother_base;
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usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
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if (!usb_base)
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return -ENOMEM;
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usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
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/* Set the PHY clock to 19.2MHz */
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v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
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v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
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v |= MX51_USB_PLL_DIV_19_2_MHZ;
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__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
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iounmap(usb_base);
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mdelay(10);
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return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
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}
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static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
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.init = initialize_otg_port,
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.portsc = MXC_EHCI_UTMI_16BIT,
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};
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static int initialize_usbh1_port(struct platform_device *pdev)
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{
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iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
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iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
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u32 v;
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void __iomem *usb_base;
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void __iomem *socregs_base;
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mxc_iomux_v3_setup_pad(usbh1gpio);
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gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
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gpio_direction_output(EFIKAMX_USBH1_STP, 0);
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msleep(1);
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gpio_set_value(EFIKAMX_USBH1_STP, 1);
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msleep(1);
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usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
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socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
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/* The clock for the USBH1 ULPI port will come externally */
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/* from the PHY. */
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v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
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__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
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socregs_base + MX51_USB_CTRL_1_OFFSET);
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iounmap(usb_base);
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gpio_free(EFIKAMX_USBH1_STP);
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mxc_iomux_v3_setup_pad(usbh1stp);
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mdelay(10);
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return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
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}
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static struct mxc_usbh_platform_data usbh1_config __initdata = {
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.init = initialize_usbh1_port,
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.portsc = MXC_EHCI_MODE_ULPI,
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};
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static void mx51_efika_hubreset(void)
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{
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gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
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gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
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msleep(1);
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gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
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msleep(1);
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gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
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}
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static void __init mx51_efika_usb(void)
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{
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mx51_efika_hubreset();
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/* pulling it low, means no USB at all... */
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gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
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gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
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msleep(1);
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gpio_set_value(EFIKA_USB_PHY_RESET, 1);
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usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
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ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
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imx51_add_mxc_ehci_otg(&dr_utmi_config);
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if (usbh1_config.otg)
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imx51_add_mxc_ehci_hs(1, &usbh1_config);
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}
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static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
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{
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.name = "u-boot",
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.offset = 0,
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.size = SZ_256K,
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},
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{
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.name = "config",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_64K,
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},
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};
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static struct flash_platform_data mx51_efika_spi_flash_data = {
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.name = "spi_flash",
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.parts = mx51_efika_spi_nor_partitions,
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.nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
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.type = "sst25vf032b",
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};
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static struct regulator_consumer_supply sw1_consumers[] = {
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{
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.supply = "cpu_vcc",
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}
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};
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static struct regulator_consumer_supply vdig_consumers[] = {
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/* sgtl5000 */
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REGULATOR_SUPPLY("VDDA", "1-000a"),
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REGULATOR_SUPPLY("VDDD", "1-000a"),
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};
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static struct regulator_consumer_supply vvideo_consumers[] = {
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/* sgtl5000 */
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REGULATOR_SUPPLY("VDDIO", "1-000a"),
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};
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static struct regulator_consumer_supply vsd_consumers[] = {
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REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
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REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
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};
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static struct regulator_consumer_supply pwgt1_consumer[] = {
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{
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.supply = "pwgt1",
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}
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};
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static struct regulator_consumer_supply pwgt2_consumer[] = {
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{
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.supply = "pwgt2",
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}
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};
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static struct regulator_consumer_supply coincell_consumer[] = {
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{
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.supply = "coincell",
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}
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};
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static struct regulator_init_data sw1_init = {
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.constraints = {
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.name = "SW1",
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.min_uV = 600000,
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.max_uV = 1375000,
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.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
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.valid_modes_mask = 0,
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.always_on = 1,
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.boot_on = 1,
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.state_mem = {
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.uV = 850000,
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.mode = REGULATOR_MODE_NORMAL,
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.enabled = 1,
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},
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},
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.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
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.consumer_supplies = sw1_consumers,
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};
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static struct regulator_init_data sw2_init = {
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.constraints = {
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.name = "SW2",
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.min_uV = 900000,
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.max_uV = 1850000,
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.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
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.always_on = 1,
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.boot_on = 1,
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.state_mem = {
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.uV = 950000,
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.mode = REGULATOR_MODE_NORMAL,
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.enabled = 1,
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},
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}
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};
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static struct regulator_init_data sw3_init = {
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.constraints = {
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.name = "SW3",
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.min_uV = 1100000,
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.max_uV = 1850000,
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.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
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.always_on = 1,
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.boot_on = 1,
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}
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};
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static struct regulator_init_data sw4_init = {
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.constraints = {
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.name = "SW4",
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.min_uV = 1100000,
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.max_uV = 1850000,
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.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
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.always_on = 1,
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.boot_on = 1,
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}
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};
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static struct regulator_init_data viohi_init = {
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.constraints = {
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.name = "VIOHI",
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.boot_on = 1,
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.always_on = 1,
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}
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};
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static struct regulator_init_data vusb_init = {
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.constraints = {
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.name = "VUSB",
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.boot_on = 1,
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.always_on = 1,
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}
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};
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static struct regulator_init_data swbst_init = {
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.constraints = {
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.name = "SWBST",
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}
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};
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static struct regulator_init_data vdig_init = {
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.constraints = {
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.name = "VDIG",
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.min_uV = 1050000,
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.max_uV = 1800000,
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.valid_ops_mask =
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REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
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.boot_on = 1,
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.always_on = 1,
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},
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.num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
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.consumer_supplies = vdig_consumers,
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};
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static struct regulator_init_data vpll_init = {
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.constraints = {
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.name = "VPLL",
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.min_uV = 1050000,
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.max_uV = 1800000,
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.valid_ops_mask =
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REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
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.boot_on = 1,
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.always_on = 1,
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}
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};
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static struct regulator_init_data vusb2_init = {
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.constraints = {
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.name = "VUSB2",
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.min_uV = 2400000,
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.max_uV = 2775000,
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.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
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.boot_on = 1,
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.always_on = 1,
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}
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};
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static struct regulator_init_data vvideo_init = {
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.constraints = {
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.name = "VVIDEO",
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.min_uV = 2775000,
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.max_uV = 2775000,
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.valid_ops_mask =
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REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
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.boot_on = 1,
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.apply_uV = 1,
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},
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.num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
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.consumer_supplies = vvideo_consumers,
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};
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static struct regulator_init_data vaudio_init = {
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.constraints = {
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.name = "VAUDIO",
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.min_uV = 2300000,
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.max_uV = 3000000,
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.valid_ops_mask =
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REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
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.boot_on = 1,
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}
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};
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static struct regulator_init_data vsd_init = {
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.constraints = {
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.name = "VSD",
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.min_uV = 1800000,
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.max_uV = 3150000,
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.valid_ops_mask =
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REGULATOR_CHANGE_VOLTAGE,
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.boot_on = 1,
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},
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.num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
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.consumer_supplies = vsd_consumers,
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};
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static struct regulator_init_data vcam_init = {
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.constraints = {
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.name = "VCAM",
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.min_uV = 2500000,
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.max_uV = 3000000,
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.valid_ops_mask =
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REGULATOR_CHANGE_VOLTAGE |
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REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
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.valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
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.boot_on = 1,
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}
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};
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static struct regulator_init_data vgen1_init = {
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.constraints = {
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.name = "VGEN1",
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.min_uV = 1200000,
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.max_uV = 3150000,
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.valid_ops_mask =
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REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
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.boot_on = 1,
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.always_on = 1,
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}
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};
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static struct regulator_init_data vgen2_init = {
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.constraints = {
|
|
.name = "VGEN2",
|
|
.min_uV = 1200000,
|
|
.max_uV = 3150000,
|
|
.valid_ops_mask =
|
|
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
|
|
.boot_on = 1,
|
|
.always_on = 1,
|
|
}
|
|
};
|
|
|
|
static struct regulator_init_data vgen3_init = {
|
|
.constraints = {
|
|
.name = "VGEN3",
|
|
.min_uV = 1800000,
|
|
.max_uV = 2900000,
|
|
.valid_ops_mask =
|
|
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
|
|
.boot_on = 1,
|
|
.always_on = 1,
|
|
}
|
|
};
|
|
|
|
static struct regulator_init_data gpo1_init = {
|
|
.constraints = {
|
|
.name = "GPO1",
|
|
}
|
|
};
|
|
|
|
static struct regulator_init_data gpo2_init = {
|
|
.constraints = {
|
|
.name = "GPO2",
|
|
}
|
|
};
|
|
|
|
static struct regulator_init_data gpo3_init = {
|
|
.constraints = {
|
|
.name = "GPO3",
|
|
}
|
|
};
|
|
|
|
static struct regulator_init_data gpo4_init = {
|
|
.constraints = {
|
|
.name = "GPO4",
|
|
}
|
|
};
|
|
|
|
static struct regulator_init_data pwgt1_init = {
|
|
.constraints = {
|
|
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
|
.boot_on = 1,
|
|
},
|
|
.num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
|
|
.consumer_supplies = pwgt1_consumer,
|
|
};
|
|
|
|
static struct regulator_init_data pwgt2_init = {
|
|
.constraints = {
|
|
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
|
.boot_on = 1,
|
|
},
|
|
.num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
|
|
.consumer_supplies = pwgt2_consumer,
|
|
};
|
|
|
|
static struct regulator_init_data vcoincell_init = {
|
|
.constraints = {
|
|
.name = "COINCELL",
|
|
.min_uV = 3000000,
|
|
.max_uV = 3000000,
|
|
.valid_ops_mask =
|
|
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
|
|
},
|
|
.num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
|
|
.consumer_supplies = coincell_consumer,
|
|
};
|
|
|
|
static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
|
|
{ .id = MC13892_SW1, .init_data = &sw1_init },
|
|
{ .id = MC13892_SW2, .init_data = &sw2_init },
|
|
{ .id = MC13892_SW3, .init_data = &sw3_init },
|
|
{ .id = MC13892_SW4, .init_data = &sw4_init },
|
|
{ .id = MC13892_SWBST, .init_data = &swbst_init },
|
|
{ .id = MC13892_VIOHI, .init_data = &viohi_init },
|
|
{ .id = MC13892_VPLL, .init_data = &vpll_init },
|
|
{ .id = MC13892_VDIG, .init_data = &vdig_init },
|
|
{ .id = MC13892_VSD, .init_data = &vsd_init },
|
|
{ .id = MC13892_VUSB2, .init_data = &vusb2_init },
|
|
{ .id = MC13892_VVIDEO, .init_data = &vvideo_init },
|
|
{ .id = MC13892_VAUDIO, .init_data = &vaudio_init },
|
|
{ .id = MC13892_VCAM, .init_data = &vcam_init },
|
|
{ .id = MC13892_VGEN1, .init_data = &vgen1_init },
|
|
{ .id = MC13892_VGEN2, .init_data = &vgen2_init },
|
|
{ .id = MC13892_VGEN3, .init_data = &vgen3_init },
|
|
{ .id = MC13892_VUSB, .init_data = &vusb_init },
|
|
{ .id = MC13892_GPO1, .init_data = &gpo1_init },
|
|
{ .id = MC13892_GPO2, .init_data = &gpo2_init },
|
|
{ .id = MC13892_GPO3, .init_data = &gpo3_init },
|
|
{ .id = MC13892_GPO4, .init_data = &gpo4_init },
|
|
{ .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init },
|
|
{ .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init },
|
|
{ .id = MC13892_VCOINCELL, .init_data = &vcoincell_init },
|
|
};
|
|
|
|
static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
|
|
.flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR,
|
|
.regulators = {
|
|
.num_regulators = ARRAY_SIZE(mx51_efika_regulators),
|
|
.regulators = mx51_efika_regulators,
|
|
},
|
|
};
|
|
|
|
static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
|
|
{
|
|
.modalias = "m25p80",
|
|
.max_speed_hz = 25000000,
|
|
.bus_num = 0,
|
|
.chip_select = 1,
|
|
.platform_data = &mx51_efika_spi_flash_data,
|
|
.irq = -1,
|
|
},
|
|
{
|
|
.modalias = "mc13892",
|
|
.max_speed_hz = 1000000,
|
|
.bus_num = 0,
|
|
.chip_select = 0,
|
|
.platform_data = &mx51_efika_mc13892_data,
|
|
.irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
|
|
},
|
|
};
|
|
|
|
static int mx51_efika_spi_cs[] = {
|
|
EFIKAMX_SPI_CS0,
|
|
EFIKAMX_SPI_CS1,
|
|
};
|
|
|
|
static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
|
|
.chipselect = mx51_efika_spi_cs,
|
|
.num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
|
|
};
|
|
|
|
void __init efika_board_common_init(void)
|
|
{
|
|
mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
|
|
ARRAY_SIZE(mx51efika_pads));
|
|
imx51_add_imx_uart(0, &uart_pdata);
|
|
mx51_efika_usb();
|
|
|
|
/* FIXME: comes from original code. check this. */
|
|
if (mx51_revision() < IMX_CHIP_REVISION_2_0)
|
|
sw2_init.constraints.state_mem.uV = 1100000;
|
|
else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
|
|
sw2_init.constraints.state_mem.uV = 1250000;
|
|
sw1_init.constraints.state_mem.uV = 1000000;
|
|
}
|
|
if (machine_is_mx51_efikasb())
|
|
vgen1_init.constraints.max_uV = 1200000;
|
|
|
|
gpio_request(EFIKAMX_PMIC, "pmic irq");
|
|
gpio_direction_input(EFIKAMX_PMIC);
|
|
spi_register_board_info(mx51_efika_spi_board_info,
|
|
ARRAY_SIZE(mx51_efika_spi_board_info));
|
|
imx51_add_ecspi(0, &mx51_efika_spi_pdata);
|
|
|
|
imx51_add_pata_imx();
|
|
|
|
#if defined(CONFIG_CPU_FREQ_IMX)
|
|
get_cpu_op = mx51_get_cpu_op;
|
|
#endif
|
|
}
|