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e83f7e02af
With Coherence Manager (CM) 3.5 information about the topology of the system, which has previously only been available through & accessed from the CM, is now also provided by the Cluster Power Controller (CPC). This includes a new CPC_CONFIG register mirroring GCR_CONFIG, and similarly a new CPC_Cx_CONFIG register mirroring GCR_Cx_CONFIG. In preparation for adjusting functions such as mips_cm_numcores(), which have previously only needed to access the CM, to also access the CPC this patch modifies the way we use the various CPS headers. Rather than having users include asm/mips-cm.h or asm/mips-cpc.h individually we instead have users include asm/mips-cps.h which in turn includes asm/mips-cm.h & asm/mips-cpc.h. This means that users will gain access to both CM & CPC registers by including one header, and most importantly it makes asm/mips-cps.h an ideal location for helper functions which need to access the various components of the CPS. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17015/ Patchwork: https://patchwork.linux-mips.org/patch/17217/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
113 lines
2.7 KiB
C
113 lines
2.7 KiB
C
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/percpu.h>
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#include <linux/spinlock.h>
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#include <asm/mips-cps.h>
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void __iomem *mips_cpc_base;
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static DEFINE_PER_CPU_ALIGNED(spinlock_t, cpc_core_lock);
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static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags);
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phys_addr_t __weak mips_cpc_default_phys_base(void)
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{
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return 0;
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}
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/**
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* mips_cpc_phys_base - retrieve the physical base address of the CPC
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*
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* This function returns the physical base address of the Cluster Power
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* Controller memory mapped registers, or 0 if no Cluster Power Controller
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* is present.
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*/
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static phys_addr_t mips_cpc_phys_base(void)
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{
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unsigned long cpc_base;
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if (!mips_cm_present())
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return 0;
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if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX))
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return 0;
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/* If the CPC is already enabled, leave it so */
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cpc_base = read_gcr_cpc_base();
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if (cpc_base & CM_GCR_CPC_BASE_CPCEN)
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return cpc_base & CM_GCR_CPC_BASE_CPCBASE;
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/* Otherwise, use the default address */
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cpc_base = mips_cpc_default_phys_base();
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if (!cpc_base)
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return cpc_base;
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/* Enable the CPC, mapped at the default address */
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write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN);
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return cpc_base;
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}
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int mips_cpc_probe(void)
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{
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phys_addr_t addr;
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unsigned int cpu;
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for_each_possible_cpu(cpu)
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spin_lock_init(&per_cpu(cpc_core_lock, cpu));
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addr = mips_cpc_phys_base();
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if (!addr)
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return -ENODEV;
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mips_cpc_base = ioremap_nocache(addr, 0x8000);
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if (!mips_cpc_base)
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return -ENXIO;
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return 0;
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}
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void mips_cpc_lock_other(unsigned int core)
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{
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unsigned int curr_core;
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if (mips_cm_revision() >= CM_REV_CM3)
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/* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
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return;
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preempt_disable();
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curr_core = cpu_core(¤t_cpu_data);
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spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
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per_cpu(cpc_core_lock_flags, curr_core));
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write_cpc_cl_other(core << __ffs(CPC_Cx_OTHER_CORENUM));
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/*
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* Ensure the core-other region reflects the appropriate core &
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* VP before any accesses to it occur.
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*/
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mb();
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}
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void mips_cpc_unlock_other(void)
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{
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unsigned int curr_core;
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if (mips_cm_revision() >= CM_REV_CM3)
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/* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
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return;
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curr_core = cpu_core(¤t_cpu_data);
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spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core),
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per_cpu(cpc_core_lock_flags, curr_core));
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preempt_enable();
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}
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