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Supports Altera SOCFPGA bridges: * fpga2sdram * fpga2hps * hps2fpga * lwhps2fpga Allows enabling/disabling the bridges through the FPGA Bridge Framework API functions. The fpga2sdram driver only supports enabling and disabling of the ports that been configured early on. This is due to a hardware limitation where the read, write, and command ports on the fpga2sdram bridge can only be reconfigured while there are no transactions to the sdram, i.e. when running out of OCRAM before the kernel boots. Device tree property 'init-val' configures the driver to enable or disable the bridge during probe. If the property does not exist, the driver will leave the bridge in its current state. Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Matthew Gerlach <mgerlach@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
53 lines
1.1 KiB
Plaintext
53 lines
1.1 KiB
Plaintext
#
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# FPGA framework configuration
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#
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menu "FPGA Configuration Support"
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config FPGA
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tristate "FPGA Configuration Framework"
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help
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Say Y here if you want support for configuring FPGAs from the
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kernel. The FPGA framework adds a FPGA manager class and FPGA
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manager drivers.
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if FPGA
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config FPGA_REGION
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tristate "FPGA Region"
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depends on OF && FPGA_BRIDGE
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help
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FPGA Regions allow loading FPGA images under control of
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the Device Tree.
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config FPGA_MGR_SOCFPGA
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tristate "Altera SOCFPGA FPGA Manager"
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depends on ARCH_SOCFPGA
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help
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FPGA manager driver support for Altera SOCFPGA.
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config FPGA_MGR_ZYNQ_FPGA
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tristate "Xilinx Zynq FPGA"
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depends on ARCH_ZYNQ || COMPILE_TEST
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depends on HAS_DMA
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help
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FPGA manager driver support for Xilinx Zynq FPGAs.
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config FPGA_BRIDGE
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tristate "FPGA Bridge Framework"
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depends on OF
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help
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Say Y here if you want to support bridges connected between host
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processors and FPGAs or between FPGAs.
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config SOCFPGA_FPGA_BRIDGE
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tristate "Altera SoCFPGA FPGA Bridges"
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depends on ARCH_SOCFPGA && FPGA_BRIDGE
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help
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Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
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devices.
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endif # FPGA
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endmenu
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