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4aa0f4d726
Interrupt Group 4 mapps the GPIO pins enabled as interrupt sources; add defines to make this clear when addressing them later in code. The mapped GPIOs support triggering on either level high or low. To achieve this, the set_type() function calls rb532_gpio_set_ilevel() for interrupts of the above mentioned group. As there is no way to alter the triggering characteristics of the other interrupts, accept level triggering on status high only. (This is just a guess; but as the system boots fine and interrupt-driven devices (e.g. serial console) work with no implications, it seems to be right.) To clear a GPIO mapped IRQ, the source has to be cleared (i.e., the interrupt status bit of the corresponding GPIO pin). This is done inside rb532_disable_irq(). After applying these changes I could undo most of my former "fixes" to pata-rb532-cf. Particularly all interrupt handling can be done generically via set_irq_type() as it was before. Signed-off-by: Phil Sutter <n0-1@freewrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
37 lines
1 KiB
C
37 lines
1 KiB
C
#ifndef __ASM_RC32434_IRQ_H
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#define __ASM_RC32434_IRQ_H
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#define NR_IRQS 256
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#include <asm/mach-generic/irq.h>
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#include <asm/mach-rc32434/rb.h>
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/* Interrupt Controller */
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#define IC_GROUP0_PEND (REGBASE + 0x38000)
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#define IC_GROUP0_MASK (REGBASE + 0x38008)
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#define IC_GROUP_OFFSET 0x0C
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#define NUM_INTR_GROUPS 5
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/* 16550 UARTs */
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#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
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/* GRP3 IRQ numbers start here */
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#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32)
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/* GRP4 IRQ numbers start here */
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#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32)
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/* GRP5 IRQ numbers start here */
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#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)
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#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
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#define UART0_IRQ (GROUP3_IRQ_BASE + 0)
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#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
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#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
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#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
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#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
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#define GPIO_MAPPED_IRQ_BASE GROUP4_IRQ_BASE
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#define GPIO_MAPPED_IRQ_GROUP 4
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#endif /* __ASM_RC32434_IRQ_H */
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