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ac5d15b451
Driver was relying on an older DPIO API, which provided a CPU-affine DPIO in case it was called with preemption disabled. Since this is no longer the case, save the CPU-affine DPIO in per-cpu private structure during setup and further use it on the hot path. Note that preemption is no longer disabled while trying to enqueue an FD. Thus it might be possible to run the enqueue on a different CPU (due to migration, when in process context), however this wouldn't be a functionality issue. Since we allow for all cores to enqueue, we take care of data structures setup to handle the case when number of (Rx, Tx) queue pairs is smaller than number of cores. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
226 lines
6.6 KiB
C
226 lines
6.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* Copyright 2015-2016 Freescale Semiconductor Inc.
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* Copyright 2017-2018 NXP
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*/
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#ifndef _CAAMALG_QI2_H_
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#define _CAAMALG_QI2_H_
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#include <soc/fsl/dpaa2-io.h>
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#include <soc/fsl/dpaa2-fd.h>
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#include <linux/threads.h>
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#include "dpseci.h"
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#include "desc_constr.h"
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#define DPAA2_CAAM_STORE_SIZE 16
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/* NAPI weight *must* be a multiple of the store size. */
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#define DPAA2_CAAM_NAPI_WEIGHT 64
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/* The congestion entrance threshold was chosen so that on LS2088
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* we support the maximum throughput for the available memory
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*/
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#define DPAA2_SEC_CONG_ENTRY_THRESH (128 * 1024 * 1024)
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#define DPAA2_SEC_CONG_EXIT_THRESH (DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10)
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/**
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* dpaa2_caam_priv - driver private data
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* @dpseci_id: DPSECI object unique ID
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* @major_ver: DPSECI major version
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* @minor_ver: DPSECI minor version
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* @dpseci_attr: DPSECI attributes
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* @sec_attr: SEC engine attributes
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* @rx_queue_attr: array of Rx queue attributes
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* @tx_queue_attr: array of Tx queue attributes
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* @cscn_mem: pointer to memory region containing the congestion SCN
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* it's size is larger than to accommodate alignment
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* @cscn_mem_aligned: pointer to congestion SCN; it is computed as
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* PTR_ALIGN(cscn_mem, DPAA2_CSCN_ALIGN)
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* @cscn_dma: dma address used by the QMAN to write CSCN messages
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* @dev: device associated with the DPSECI object
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* @mc_io: pointer to MC portal's I/O object
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* @domain: IOMMU domain
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* @ppriv: per CPU pointers to privata data
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*/
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struct dpaa2_caam_priv {
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int dpsec_id;
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u16 major_ver;
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u16 minor_ver;
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struct dpseci_attr dpseci_attr;
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struct dpseci_sec_attr sec_attr;
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struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_MAX_QUEUE_NUM];
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struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_MAX_QUEUE_NUM];
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int num_pairs;
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/* congestion */
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void *cscn_mem;
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void *cscn_mem_aligned;
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dma_addr_t cscn_dma;
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struct device *dev;
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struct fsl_mc_io *mc_io;
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struct iommu_domain *domain;
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struct dpaa2_caam_priv_per_cpu __percpu *ppriv;
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};
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/**
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* dpaa2_caam_priv_per_cpu - per CPU private data
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* @napi: napi structure
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* @net_dev: netdev used by napi
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* @req_fqid: (virtual) request (Tx / enqueue) FQID
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* @rsp_fqid: (virtual) response (Rx / dequeue) FQID
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* @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr
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* @nctx: notification context of response FQ
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* @store: where dequeued frames are stored
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* @priv: backpointer to dpaa2_caam_priv
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* @dpio: portal used for data path operations
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*/
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struct dpaa2_caam_priv_per_cpu {
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struct napi_struct napi;
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struct net_device net_dev;
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int req_fqid;
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int rsp_fqid;
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int prio;
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struct dpaa2_io_notification_ctx nctx;
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struct dpaa2_io_store *store;
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struct dpaa2_caam_priv *priv;
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struct dpaa2_io *dpio;
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};
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/*
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* The CAAM QI hardware constructs a job descriptor which points
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* to shared descriptor (as pointed by context_a of FQ to CAAM).
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* When the job descriptor is executed by deco, the whole job
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* descriptor together with shared descriptor gets loaded in
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* deco buffer which is 64 words long (each 32-bit).
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*
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* The job descriptor constructed by QI hardware has layout:
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*
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* HEADER (1 word)
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* Shdesc ptr (1 or 2 words)
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* SEQ_OUT_PTR (1 word)
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* Out ptr (1 or 2 words)
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* Out length (1 word)
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* SEQ_IN_PTR (1 word)
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* In ptr (1 or 2 words)
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* In length (1 word)
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*
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* The shdesc ptr is used to fetch shared descriptor contents
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* into deco buffer.
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*
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* Apart from shdesc contents, the total number of words that
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* get loaded in deco buffer are '8' or '11'. The remaining words
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* in deco buffer can be used for storing shared descriptor.
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*/
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#define MAX_SDLEN ((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / CAAM_CMD_SZ)
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/* Length of a single buffer in the QI driver memory cache */
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#define CAAM_QI_MEMCACHE_SIZE 512
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/*
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* aead_edesc - s/w-extended aead descriptor
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* @src_nents: number of segments in input scatterlist
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* @dst_nents: number of segments in output scatterlist
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* @iv_dma: dma address of iv for checking continuity and link table
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* @qm_sg_bytes: length of dma mapped h/w link table
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* @qm_sg_dma: bus physical mapped address of h/w link table
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* @assoclen: associated data length, in CAAM endianness
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* @assoclen_dma: bus physical mapped address of req->assoclen
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* @sgt: the h/w link table, followed by IV
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*/
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struct aead_edesc {
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int src_nents;
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int dst_nents;
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dma_addr_t iv_dma;
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int qm_sg_bytes;
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dma_addr_t qm_sg_dma;
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unsigned int assoclen;
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dma_addr_t assoclen_dma;
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struct dpaa2_sg_entry sgt[0];
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};
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/*
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* skcipher_edesc - s/w-extended skcipher descriptor
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* @src_nents: number of segments in input scatterlist
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* @dst_nents: number of segments in output scatterlist
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* @iv_dma: dma address of iv for checking continuity and link table
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* @qm_sg_bytes: length of dma mapped qm_sg space
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* @qm_sg_dma: I/O virtual address of h/w link table
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* @sgt: the h/w link table, followed by IV
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*/
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struct skcipher_edesc {
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int src_nents;
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int dst_nents;
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dma_addr_t iv_dma;
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int qm_sg_bytes;
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dma_addr_t qm_sg_dma;
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struct dpaa2_sg_entry sgt[0];
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};
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/*
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* ahash_edesc - s/w-extended ahash descriptor
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* @dst_dma: I/O virtual address of req->result
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* @qm_sg_dma: I/O virtual address of h/w link table
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* @src_nents: number of segments in input scatterlist
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* @qm_sg_bytes: length of dma mapped qm_sg space
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* @sgt: pointer to h/w link table
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*/
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struct ahash_edesc {
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dma_addr_t dst_dma;
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dma_addr_t qm_sg_dma;
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int src_nents;
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int qm_sg_bytes;
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struct dpaa2_sg_entry sgt[0];
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};
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/**
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* caam_flc - Flow Context (FLC)
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* @flc: Flow Context options
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* @sh_desc: Shared Descriptor
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*/
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struct caam_flc {
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u32 flc[16];
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u32 sh_desc[MAX_SDLEN];
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} ____cacheline_aligned;
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enum optype {
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ENCRYPT = 0,
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DECRYPT,
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NUM_OP
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};
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/**
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* caam_request - the request structure the driver application should fill while
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* submitting a job to driver.
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* @fd_flt: Frame list table defining input and output
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* fd_flt[0] - FLE pointing to output buffer
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* fd_flt[1] - FLE pointing to input buffer
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* @fd_flt_dma: DMA address for the frame list table
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* @flc: Flow Context
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* @flc_dma: I/O virtual address of Flow Context
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* @cbk: Callback function to invoke when job is completed
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* @ctx: arbit context attached with request by the application
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* @edesc: extended descriptor; points to one of {skcipher,aead}_edesc
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*/
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struct caam_request {
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struct dpaa2_fl_entry fd_flt[2];
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dma_addr_t fd_flt_dma;
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struct caam_flc *flc;
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dma_addr_t flc_dma;
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void (*cbk)(void *ctx, u32 err);
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void *ctx;
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void *edesc;
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};
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/**
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* dpaa2_caam_enqueue() - enqueue a crypto request
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* @dev: device associated with the DPSECI object
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* @req: pointer to caam_request
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*/
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int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);
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#endif /* _CAAMALG_QI2_H_ */
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