linux/arch/mips/alchemy
Thomas Gleixner e0288a0a7b MIPS: alchemy: Remove pointless irqdisable/enable
bcsr_csc_handler() is a cascading interrupt handler. It has a
disable_irq_nosync()/enable_irq() pair around the generic_handle_irq()
call. The value of this disable/enable is zero because its a complete
noop:

disable_irq_nosync() merily increments the disable count without
actually masking the interrupt. enable_irq() soleley decrements the
disable count without touching the interrupt chip. The interrupt
cannot arrive again because the complete call chain runs with
interrupts disabled.

Remove it.

[ralf@linux-mips.org: Fold in followup fix from Thomas Gleixner.]

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Cc: LKML <linux-kernel@vger.kernel.org>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
Patchwork: https://patchwork.linux-mips.org/patch/10702/
Patchwork: https://patchwork.linux-mips.org/patch/10708/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-08-26 15:23:30 +02:00
..
common MIPS: alchemy: Use irq_set_chip_handler_name_locked() 2015-08-26 15:23:28 +02:00
devboards MIPS: alchemy: Remove pointless irqdisable/enable 2015-08-26 15:23:30 +02:00
board-gpr.c MIPS: Alchemy: Fix unchecked kstrtoul return value 2014-03-06 20:52:28 +01:00
board-mtx1.c MIPS: Alchemy: introduce helpers to access SYS register block. 2014-07-30 13:53:28 +02:00
board-xxs1500.c MIPS: Alchemy: introduce helpers to access SYS register block. 2014-07-30 13:53:28 +02:00
Kconfig MIPS: Alchemy: Unify Devboard support. 2014-03-26 23:09:21 +01:00
Makefile MIPS: Alchemy: merge GPR/MTX-1/XXS1500 board code into single files 2011-12-07 22:02:06 +00:00
Platform MIPS: Alchemy: Unify Devboard support. 2014-03-26 23:09:21 +01:00