mirror of
https://github.com/torvalds/linux
synced 2024-09-20 02:57:25 +00:00
0ae2d26ffe
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated. Also address the "Programming Note" for optimal performance. Here is the complete text from Oracle SPARC Architecture Specs. 6.3.4.7 DCTI Couples "A delayed control transfer instruction (DCTI) in the delay slot of another DCTI is referred to as a “DCTI couple”. The use of DCTI couples is deprecated in the Oracle SPARC Architecture; no new software should place a DCTI in the delay slot of another DCTI, because on future Oracle SPARC Architecture implementations DCTI couples may execute either slowly or differently than the programmer assumes it will. SPARC V8 and SPARC V9 Compatibility Note The SPARC V8 architecture left behavior undefined for a DCTI couple. The SPARC V9 architecture defined behavior in that case, but as of UltraSPARC Architecture 2005, use of DCTI couples was deprecated. Software should not expect high performance from DCTI couples, and performance of DCTI couples should be expected to decline further in future processors. Programming Note As noted in TABLE 6-5 on page 115, an annulled branch-always (branch-always with a = 1) instruction is not architecturally a DCTI. However, since not all implementations make that distinction, for optimal performance, a DCTI should not be placed in the instruction word immediately following an annulled branch-always instruction (BA,A or BPA,A)." Signed-off-by: Babu Moger <babu.moger@oracle.com> Reviewed-by: Rob Gardner <rob.gardner@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
107 lines
2.2 KiB
ArmAsm
107 lines
2.2 KiB
ArmAsm
/* NG4memset.S: Niagara-4 optimized memset/bzero.
|
|
*
|
|
* Copyright (C) 2012 David S. Miller (davem@davemloft.net)
|
|
*/
|
|
|
|
#include <asm/asi.h>
|
|
|
|
.register %g2, #scratch
|
|
.register %g3, #scratch
|
|
|
|
.text
|
|
.align 32
|
|
.globl NG4memset
|
|
NG4memset:
|
|
andcc %o1, 0xff, %o4
|
|
be,pt %icc, 1f
|
|
mov %o2, %o1
|
|
sllx %o4, 8, %g1
|
|
or %g1, %o4, %o2
|
|
sllx %o2, 16, %g1
|
|
or %g1, %o2, %o2
|
|
sllx %o2, 32, %g1
|
|
ba,pt %icc, 1f
|
|
or %g1, %o2, %o4
|
|
.size NG4memset,.-NG4memset
|
|
|
|
.align 32
|
|
.globl NG4bzero
|
|
NG4bzero:
|
|
clr %o4
|
|
1: cmp %o1, 16
|
|
ble %icc, .Ltiny
|
|
mov %o0, %o3
|
|
sub %g0, %o0, %g1
|
|
and %g1, 0x7, %g1
|
|
brz,pt %g1, .Laligned8
|
|
sub %o1, %g1, %o1
|
|
1: stb %o4, [%o0 + 0x00]
|
|
subcc %g1, 1, %g1
|
|
bne,pt %icc, 1b
|
|
add %o0, 1, %o0
|
|
.Laligned8:
|
|
cmp %o1, 64 + (64 - 8)
|
|
ble .Lmedium
|
|
sub %g0, %o0, %g1
|
|
andcc %g1, (64 - 1), %g1
|
|
brz,pn %g1, .Laligned64
|
|
sub %o1, %g1, %o1
|
|
1: stx %o4, [%o0 + 0x00]
|
|
subcc %g1, 8, %g1
|
|
bne,pt %icc, 1b
|
|
add %o0, 0x8, %o0
|
|
.Laligned64:
|
|
andn %o1, 64 - 1, %g1
|
|
sub %o1, %g1, %o1
|
|
brnz,pn %o4, .Lnon_bzero_loop
|
|
mov 0x20, %g2
|
|
1: stxa %o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
|
|
subcc %g1, 0x40, %g1
|
|
stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
|
|
bne,pt %icc, 1b
|
|
add %o0, 0x40, %o0
|
|
.Lpostloop:
|
|
cmp %o1, 8
|
|
bl,pn %icc, .Ltiny
|
|
membar #StoreStore|#StoreLoad
|
|
.Lmedium:
|
|
andn %o1, 0x7, %g1
|
|
sub %o1, %g1, %o1
|
|
1: stx %o4, [%o0 + 0x00]
|
|
subcc %g1, 0x8, %g1
|
|
bne,pt %icc, 1b
|
|
add %o0, 0x08, %o0
|
|
andcc %o1, 0x4, %g1
|
|
be,pt %icc, .Ltiny
|
|
sub %o1, %g1, %o1
|
|
stw %o4, [%o0 + 0x00]
|
|
add %o0, 0x4, %o0
|
|
.Ltiny:
|
|
cmp %o1, 0
|
|
be,pn %icc, .Lexit
|
|
1: subcc %o1, 1, %o1
|
|
stb %o4, [%o0 + 0x00]
|
|
bne,pt %icc, 1b
|
|
add %o0, 1, %o0
|
|
.Lexit:
|
|
retl
|
|
mov %o3, %o0
|
|
.Lnon_bzero_loop:
|
|
mov 0x08, %g3
|
|
mov 0x28, %o5
|
|
1: stxa %o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
|
|
subcc %g1, 0x40, %g1
|
|
stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
|
|
stxa %o4, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
|
|
stxa %o4, [%o0 + %o5] ASI_BLK_INIT_QUAD_LDD_P
|
|
add %o0, 0x10, %o0
|
|
stxa %o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
|
|
stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
|
|
stxa %o4, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
|
|
stxa %o4, [%o0 + %o5] ASI_BLK_INIT_QUAD_LDD_P
|
|
bne,pt %icc, 1b
|
|
add %o0, 0x30, %o0
|
|
ba,a,pt %icc, .Lpostloop
|
|
nop
|
|
.size NG4bzero,.-NG4bzero
|