linux/drivers/pnp/quirks.c
Josh Boyer ed1f0eeeba PNP: Add Haswell-ULT to Intel MCH size workaround
Add device ID 0x0a04 for Haswell-ULT to the list of devices with MCH
problems.

From a Lenovo ThinkPad T440S:
[    0.188604] pnp: PnP ACPI init
[    0.189044] system 00:00: [mem 0x00000000-0x0009ffff] could not be reserved
[    0.189048] system 00:00: [mem 0x000c0000-0x000c3fff] could not be reserved
[    0.189050] system 00:00: [mem 0x000c4000-0x000c7fff] could not be reserved
[    0.189052] system 00:00: [mem 0x000c8000-0x000cbfff] could not be reserved
[    0.189054] system 00:00: [mem 0x000cc000-0x000cffff] could not be reserved
[    0.189056] system 00:00: [mem 0x000d0000-0x000d3fff] has been reserved
[    0.189058] system 00:00: [mem 0x000d4000-0x000d7fff] has been reserved
[    0.189060] system 00:00: [mem 0x000d8000-0x000dbfff] has been reserved
[    0.189061] system 00:00: [mem 0x000dc000-0x000dffff] has been reserved
[    0.189063] system 00:00: [mem 0x000e0000-0x000e3fff] could not be reserved
[    0.189065] system 00:00: [mem 0x000e4000-0x000e7fff] could not be reserved
[    0.189067] system 00:00: [mem 0x000e8000-0x000ebfff] could not be reserved
[    0.189069] system 00:00: [mem 0x000ec000-0x000effff] could not be reserved
[    0.189071] system 00:00: [mem 0x000f0000-0x000fffff] could not be reserved
[    0.189073] system 00:00: [mem 0x00100000-0xdf9fffff] could not be reserved
[    0.189075] system 00:00: [mem 0xfec00000-0xfed3ffff] could not be reserved
[    0.189078] system 00:00: [mem 0xfed4c000-0xffffffff] could not be reserved
[    0.189082] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active)
[    0.189216] system 00:01: [io  0x1800-0x189f] could not be reserved
[    0.189220] system 00:01: [io  0x0800-0x087f] has been reserved
[    0.189222] system 00:01: [io  0x0880-0x08ff] has been reserved
[    0.189224] system 00:01: [io  0x0900-0x097f] has been reserved
[    0.189226] system 00:01: [io  0x0980-0x09ff] has been reserved
[    0.189229] system 00:01: [io  0x0a00-0x0a7f] has been reserved
[    0.189231] system 00:01: [io  0x0a80-0x0aff] has been reserved
[    0.189233] system 00:01: [io  0x0b00-0x0b7f] has been reserved
[    0.189235] system 00:01: [io  0x0b80-0x0bff] has been reserved
[    0.189238] system 00:01: [io  0x15e0-0x15ef] has been reserved
[    0.189240] system 00:01: [io  0x1600-0x167f] has been reserved
[    0.189242] system 00:01: [io  0x1640-0x165f] has been reserved
[    0.189246] system 00:01: [mem 0xf8000000-0xfbffffff] could not be reserved
[    0.189249] system 00:01: [mem 0x00000000-0x00000fff] could not be reserved
[    0.189251] system 00:01: [mem 0xfed1c000-0xfed1ffff] has been reserved
[    0.189254] system 00:01: [mem 0xfed10000-0xfed13fff] has been reserved
[    0.189256] system 00:01: [mem 0xfed18000-0xfed18fff] has been reserved
[    0.189258] system 00:01: [mem 0xfed19000-0xfed19fff] has been reserved
[    0.189261] system 00:01: [mem 0xfed45000-0xfed4bfff] has been reserved
[    0.189264] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
[....]
[    0.583653] resource sanity check: requesting [mem 0xfed10000-0xfed15fff], which spans more than pnp 00:01 [mem 0xfed10000-0xfed13fff]
[    0.583654] ------------[ cut here ]------------
[    0.583660] WARNING: CPU: 0 PID: 1 at arch/x86/mm/ioremap.c:198 __ioremap_caller+0x2c5/0x380()
[    0.583661] Info: mapping multiple BARs. Your kernel is fine.
[    0.583662] Modules linked in:

[    0.583666] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.3.3-303.fc23.x86_64 #1
[    0.583668] Hardware name: LENOVO 20AR001GXS/20AR001GXS, BIOS GJET86WW (2.36 ) 12/04/2015
[    0.583670]  0000000000000000 0000000014cf7e59 ffff880214a1baf8 ffffffff813a625f
[    0.583673]  ffff880214a1bb40 ffff880214a1bb30 ffffffff810a07c2 00000000fed10000
[    0.583675]  ffffc90000cb8000 0000000000006000 0000000000000000 ffff8800d6381040
[    0.583678] Call Trace:
[    0.583683]  [<ffffffff813a625f>] dump_stack+0x44/0x55
[    0.583686]  [<ffffffff810a07c2>] warn_slowpath_common+0x82/0xc0
[    0.583688]  [<ffffffff810a085c>] warn_slowpath_fmt+0x5c/0x80
[    0.583692]  [<ffffffff810a6fba>] ? iomem_map_sanity_check+0xba/0xd0
[    0.583695]  [<ffffffff81065835>] __ioremap_caller+0x2c5/0x380
[    0.583698]  [<ffffffff81065907>] ioremap_nocache+0x17/0x20
[    0.583701]  [<ffffffff8103a119>] snb_uncore_imc_init_box+0x79/0xb0
[    0.583705]  [<ffffffff81038900>] uncore_pci_probe+0xd0/0x1b0
[    0.583707]  [<ffffffff813efda5>] local_pci_probe+0x45/0xa0
[    0.583710]  [<ffffffff813f118d>] pci_device_probe+0xfd/0x140
[    0.583713]  [<ffffffff814d9b52>] driver_probe_device+0x222/0x480
[    0.583715]  [<ffffffff814d9e34>] __driver_attach+0x84/0x90
[    0.583717]  [<ffffffff814d9db0>] ? driver_probe_device+0x480/0x480
[    0.583720]  [<ffffffff814d762c>] bus_for_each_dev+0x6c/0xc0
[    0.583722]  [<ffffffff814d930e>] driver_attach+0x1e/0x20
[    0.583724]  [<ffffffff814d8e4b>] bus_add_driver+0x1eb/0x280
[    0.583727]  [<ffffffff81d6af1a>] ? uncore_cpu_setup+0x12/0x12
[    0.583729]  [<ffffffff814da680>] driver_register+0x60/0xe0
[    0.583733]  [<ffffffff813ef78c>] __pci_register_driver+0x4c/0x50
[    0.583736]  [<ffffffff81d6affc>] intel_uncore_init+0xe2/0x2e6
[    0.583738]  [<ffffffff81d6af1a>] ? uncore_cpu_setup+0x12/0x12
[    0.583741]  [<ffffffff81002123>] do_one_initcall+0xb3/0x200
[    0.583745]  [<ffffffff810be500>] ? parse_args+0x1a0/0x4a0
[    0.583749]  [<ffffffff81d5c1c8>] kernel_init_freeable+0x189/0x223
[    0.583752]  [<ffffffff81775c40>] ? rest_init+0x80/0x80
[    0.583754]  [<ffffffff81775c4e>] kernel_init+0xe/0xe0
[    0.583758]  [<ffffffff81781adf>] ret_from_fork+0x3f/0x70
[    0.583760]  [<ffffffff81775c40>] ? rest_init+0x80/0x80
[    0.583765] ---[ end trace 077c426a39e018aa ]---

00:00.0 Host bridge [0600]: Intel Corporation Haswell-ULT DRAM Controller [8086:0a04] (rev 0b)
	Subsystem: Lenovo Device [17aa:220c]
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
	Latency: 0
	Capabilities: <access denied>
	Kernel driver in use: hsw_uncore

Link: https://bugzilla.redhat.com/show_bug.cgi?id=1300955
Tested-by: <robo@tcp.sk>
Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2016-02-03 01:00:29 +01:00

466 lines
12 KiB
C

/*
* This file contains quirk handling code for PnP devices
* Some devices do not report all their resources, and need to have extra
* resources added. This is most easily accomplished at initialisation time
* when building up the resource structure for the first time.
*
* Copyright (c) 2000 Peter Denison <peterd@pnd-pc.demon.co.uk>
* Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
* Bjorn Helgaas <bjorn.helgaas@hp.com>
*
* Heavily based on PCI quirks handling which is
*
* Copyright (c) 1999 Martin Mares <mj@ucw.cz>
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/pnp.h>
#include <linux/io.h>
#include <linux/kallsyms.h>
#include "base.h"
static void quirk_awe32_add_ports(struct pnp_dev *dev,
struct pnp_option *option,
unsigned int offset)
{
struct pnp_option *new_option;
new_option = kmalloc(sizeof(struct pnp_option), GFP_KERNEL);
if (!new_option) {
dev_err(&dev->dev, "couldn't add ioport region to option set "
"%d\n", pnp_option_set(option));
return;
}
*new_option = *option;
new_option->u.port.min += offset;
new_option->u.port.max += offset;
list_add(&new_option->list, &option->list);
dev_info(&dev->dev, "added ioport region %#llx-%#llx to set %d\n",
(unsigned long long) new_option->u.port.min,
(unsigned long long) new_option->u.port.max,
pnp_option_set(option));
}
static void quirk_awe32_resources(struct pnp_dev *dev)
{
struct pnp_option *option;
unsigned int set = ~0;
/*
* Add two extra ioport regions (at offset 0x400 and 0x800 from the
* one given) to every dependent option set.
*/
list_for_each_entry(option, &dev->options, list) {
if (pnp_option_is_dependent(option) &&
pnp_option_set(option) != set) {
set = pnp_option_set(option);
quirk_awe32_add_ports(dev, option, 0x800);
quirk_awe32_add_ports(dev, option, 0x400);
}
}
}
static void quirk_cmi8330_resources(struct pnp_dev *dev)
{
struct pnp_option *option;
struct pnp_irq *irq;
struct pnp_dma *dma;
list_for_each_entry(option, &dev->options, list) {
if (!pnp_option_is_dependent(option))
continue;
if (option->type == IORESOURCE_IRQ) {
irq = &option->u.irq;
bitmap_zero(irq->map.bits, PNP_IRQ_NR);
__set_bit(5, irq->map.bits);
__set_bit(7, irq->map.bits);
__set_bit(10, irq->map.bits);
dev_info(&dev->dev, "set possible IRQs in "
"option set %d to 5, 7, 10\n",
pnp_option_set(option));
} else if (option->type == IORESOURCE_DMA) {
dma = &option->u.dma;
if ((dma->flags & IORESOURCE_DMA_TYPE_MASK) ==
IORESOURCE_DMA_8BIT &&
dma->map != 0x0A) {
dev_info(&dev->dev, "changing possible "
"DMA channel mask in option set %d "
"from %#02x to 0x0A (1, 3)\n",
pnp_option_set(option), dma->map);
dma->map = 0x0A;
}
}
}
}
static void quirk_sb16audio_resources(struct pnp_dev *dev)
{
struct pnp_option *option;
unsigned int prev_option_flags = ~0, n = 0;
struct pnp_port *port;
/*
* The default range on the OPL port for these devices is 0x388-0x388.
* Here we increase that range so that two such cards can be
* auto-configured.
*/
list_for_each_entry(option, &dev->options, list) {
if (prev_option_flags != option->flags) {
prev_option_flags = option->flags;
n = 0;
}
if (pnp_option_is_dependent(option) &&
option->type == IORESOURCE_IO) {
n++;
port = &option->u.port;
if (n == 3 && port->min == port->max) {
port->max += 0x70;
dev_info(&dev->dev, "increased option port "
"range from %#llx-%#llx to "
"%#llx-%#llx\n",
(unsigned long long) port->min,
(unsigned long long) port->min,
(unsigned long long) port->min,
(unsigned long long) port->max);
}
}
}
}
static struct pnp_option *pnp_clone_dependent_set(struct pnp_dev *dev,
unsigned int set)
{
struct pnp_option *tail = NULL, *first_new_option = NULL;
struct pnp_option *option, *new_option;
unsigned int flags;
list_for_each_entry(option, &dev->options, list) {
if (pnp_option_is_dependent(option))
tail = option;
}
if (!tail) {
dev_err(&dev->dev, "no dependent option sets\n");
return NULL;
}
flags = pnp_new_dependent_set(dev, PNP_RES_PRIORITY_FUNCTIONAL);
list_for_each_entry(option, &dev->options, list) {
if (pnp_option_is_dependent(option) &&
pnp_option_set(option) == set) {
new_option = kmalloc(sizeof(struct pnp_option),
GFP_KERNEL);
if (!new_option) {
dev_err(&dev->dev, "couldn't clone dependent "
"set %d\n", set);
return NULL;
}
*new_option = *option;
new_option->flags = flags;
if (!first_new_option)
first_new_option = new_option;
list_add(&new_option->list, &tail->list);
tail = new_option;
}
}
return first_new_option;
}
static void quirk_add_irq_optional_dependent_sets(struct pnp_dev *dev)
{
struct pnp_option *new_option;
unsigned int num_sets, i, set;
struct pnp_irq *irq;
num_sets = dev->num_dependent_sets;
for (i = 0; i < num_sets; i++) {
new_option = pnp_clone_dependent_set(dev, i);
if (!new_option)
return;
set = pnp_option_set(new_option);
while (new_option && pnp_option_set(new_option) == set) {
if (new_option->type == IORESOURCE_IRQ) {
irq = &new_option->u.irq;
irq->flags |= IORESOURCE_IRQ_OPTIONAL;
}
dbg_pnp_show_option(dev, new_option);
new_option = list_entry(new_option->list.next,
struct pnp_option, list);
}
dev_info(&dev->dev, "added dependent option set %d (same as "
"set %d except IRQ optional)\n", set, i);
}
}
static void quirk_ad1815_mpu_resources(struct pnp_dev *dev)
{
struct pnp_option *option;
struct pnp_irq *irq = NULL;
unsigned int independent_irqs = 0;
list_for_each_entry(option, &dev->options, list) {
if (option->type == IORESOURCE_IRQ &&
!pnp_option_is_dependent(option)) {
independent_irqs++;
irq = &option->u.irq;
}
}
if (independent_irqs != 1)
return;
irq->flags |= IORESOURCE_IRQ_OPTIONAL;
dev_info(&dev->dev, "made independent IRQ optional\n");
}
#include <linux/pci.h>
static void quirk_system_pci_resources(struct pnp_dev *dev)
{
struct pci_dev *pdev = NULL;
struct resource *res;
resource_size_t pnp_start, pnp_end, pci_start, pci_end;
int i, j;
/*
* Some BIOSes have PNP motherboard devices with resources that
* partially overlap PCI BARs. The PNP system driver claims these
* motherboard resources, which prevents the normal PCI driver from
* requesting them later.
*
* This patch disables the PNP resources that conflict with PCI BARs
* so they won't be claimed by the PNP system driver.
*/
for_each_pci_dev(pdev) {
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
unsigned long flags, type;
flags = pci_resource_flags(pdev, i);
type = flags & (IORESOURCE_IO | IORESOURCE_MEM);
if (!type || pci_resource_len(pdev, i) == 0)
continue;
if (flags & IORESOURCE_UNSET)
continue;
pci_start = pci_resource_start(pdev, i);
pci_end = pci_resource_end(pdev, i);
for (j = 0;
(res = pnp_get_resource(dev, type, j)); j++) {
if (res->start == 0 && res->end == 0)
continue;
pnp_start = res->start;
pnp_end = res->end;
/*
* If the PNP region doesn't overlap the PCI
* region at all, there's no problem.
*/
if (pnp_end < pci_start || pnp_start > pci_end)
continue;
/*
* If the PNP region completely encloses (or is
* at least as large as) the PCI region, that's
* also OK. For example, this happens when the
* PNP device describes a bridge with PCI
* behind it.
*/
if (pnp_start <= pci_start &&
pnp_end >= pci_end)
continue;
/*
* Otherwise, the PNP region overlaps *part* of
* the PCI region, and that might prevent a PCI
* driver from requesting its resources.
*/
dev_warn(&dev->dev,
"disabling %pR because it overlaps "
"%s BAR %d %pR\n", res,
pci_name(pdev), i, &pdev->resource[i]);
res->flags |= IORESOURCE_DISABLED;
}
}
}
}
#ifdef CONFIG_AMD_NB
#include <asm/amd_nb.h>
static void quirk_amd_mmconfig_area(struct pnp_dev *dev)
{
resource_size_t start, end;
struct pnp_resource *pnp_res;
struct resource *res;
struct resource mmconfig_res, *mmconfig;
mmconfig = amd_get_mmconfig_range(&mmconfig_res);
if (!mmconfig)
return;
list_for_each_entry(pnp_res, &dev->resources, list) {
res = &pnp_res->res;
if (res->end < mmconfig->start || res->start > mmconfig->end ||
(res->start == mmconfig->start && res->end == mmconfig->end))
continue;
dev_info(&dev->dev, FW_BUG
"%pR covers only part of AMD MMCONFIG area %pR; adding more reservations\n",
res, mmconfig);
if (mmconfig->start < res->start) {
start = mmconfig->start;
end = res->start - 1;
pnp_add_mem_resource(dev, start, end, 0);
}
if (mmconfig->end > res->end) {
start = res->end + 1;
end = mmconfig->end;
pnp_add_mem_resource(dev, start, end, 0);
}
break;
}
}
#endif
#ifdef CONFIG_PCI
/* Device IDs of parts that have 32KB MCH space */
static const unsigned int mch_quirk_devices[] = {
0x0154, /* Ivy Bridge */
0x0a04, /* Haswell-ULT */
0x0c00, /* Haswell */
0x1604, /* Broadwell */
};
static struct pci_dev *get_intel_host(void)
{
int i;
struct pci_dev *host;
for (i = 0; i < ARRAY_SIZE(mch_quirk_devices); i++) {
host = pci_get_device(PCI_VENDOR_ID_INTEL, mch_quirk_devices[i],
NULL);
if (host)
return host;
}
return NULL;
}
static void quirk_intel_mch(struct pnp_dev *dev)
{
struct pci_dev *host;
u32 addr_lo, addr_hi;
struct pci_bus_region region;
struct resource mch;
struct pnp_resource *pnp_res;
struct resource *res;
host = get_intel_host();
if (!host)
return;
/*
* MCHBAR is not an architected PCI BAR, so MCH space is usually
* reported as a PNP0C02 resource. The MCH space was originally
* 16KB, but is 32KB in newer parts. Some BIOSes still report a
* PNP0C02 resource that is only 16KB, which means the rest of the
* MCH space is consumed but unreported.
*/
/*
* Read MCHBAR for Host Member Mapped Register Range Base
* https://www-ssl.intel.com/content/www/us/en/processors/core/4th-gen-core-family-desktop-vol-2-datasheet
* Sec 3.1.12.
*/
pci_read_config_dword(host, 0x48, &addr_lo);
region.start = addr_lo & ~0x7fff;
pci_read_config_dword(host, 0x4c, &addr_hi);
region.start |= (u64) addr_hi << 32;
region.end = region.start + 32*1024 - 1;
memset(&mch, 0, sizeof(mch));
mch.flags = IORESOURCE_MEM;
pcibios_bus_to_resource(host->bus, &mch, &region);
list_for_each_entry(pnp_res, &dev->resources, list) {
res = &pnp_res->res;
if (res->end < mch.start || res->start > mch.end)
continue; /* no overlap */
if (res->start == mch.start && res->end == mch.end)
continue; /* exact match */
dev_info(&dev->dev, FW_BUG "PNP resource %pR covers only part of %s Intel MCH; extending to %pR\n",
res, pci_name(host), &mch);
res->start = mch.start;
res->end = mch.end;
break;
}
pci_dev_put(host);
}
#endif
/*
* PnP Quirks
* Cards or devices that need some tweaking due to incomplete resource info
*/
static struct pnp_fixup pnp_fixups[] = {
/* Soundblaster awe io port quirk */
{"CTL0021", quirk_awe32_resources},
{"CTL0022", quirk_awe32_resources},
{"CTL0023", quirk_awe32_resources},
/* CMI 8330 interrupt and dma fix */
{"@X@0001", quirk_cmi8330_resources},
/* Soundblaster audio device io port range quirk */
{"CTL0001", quirk_sb16audio_resources},
{"CTL0031", quirk_sb16audio_resources},
{"CTL0041", quirk_sb16audio_resources},
{"CTL0042", quirk_sb16audio_resources},
{"CTL0043", quirk_sb16audio_resources},
{"CTL0044", quirk_sb16audio_resources},
{"CTL0045", quirk_sb16audio_resources},
/* Add IRQ-optional MPU options */
{"ADS7151", quirk_ad1815_mpu_resources},
{"ADS7181", quirk_add_irq_optional_dependent_sets},
{"AZT0002", quirk_add_irq_optional_dependent_sets},
/* PnP resources that might overlap PCI BARs */
{"PNP0c01", quirk_system_pci_resources},
{"PNP0c02", quirk_system_pci_resources},
#ifdef CONFIG_AMD_NB
{"PNP0c01", quirk_amd_mmconfig_area},
#endif
#ifdef CONFIG_PCI
{"PNP0c02", quirk_intel_mch},
#endif
{""}
};
void pnp_fixup_device(struct pnp_dev *dev)
{
struct pnp_fixup *f;
for (f = pnp_fixups; *f->id; f++) {
if (!compare_pnp_id(dev->id, f->id))
continue;
pnp_dbg(&dev->dev, "%s: calling %pF\n", f->id,
f->quirk_function);
f->quirk_function(dev);
}
}