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https://github.com/torvalds/linux
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![H. Peter Anvin (Intel)](/assets/img/avatar_default.png)
Update the objtool decoder to know about the ERET[US] instructions (type INSN_CONTEXT_SWITCH). Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com> Signed-off-by: Xin Li <xin3.li@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Shan Kang <shan.kang@intel.com> Link: https://lore.kernel.org/r/20231205105030.8698-11-xin3.li@intel.com
844 lines
16 KiB
C
844 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2015 Josh Poimboeuf <jpoimboe@redhat.com>
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#define unlikely(cond) (cond)
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#include <asm/insn.h>
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#include "../../../arch/x86/lib/inat.c"
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#include "../../../arch/x86/lib/insn.c"
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#define CONFIG_64BIT 1
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#include <asm/nops.h>
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#include <asm/orc_types.h>
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#include <objtool/check.h>
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#include <objtool/elf.h>
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#include <objtool/arch.h>
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#include <objtool/warn.h>
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#include <objtool/endianness.h>
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#include <objtool/builtin.h>
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#include <arch/elf.h>
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int arch_ftrace_match(char *name)
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{
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return !strcmp(name, "__fentry__");
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}
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static int is_x86_64(const struct elf *elf)
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{
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switch (elf->ehdr.e_machine) {
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case EM_X86_64:
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return 1;
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case EM_386:
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return 0;
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default:
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WARN("unexpected ELF machine type %d", elf->ehdr.e_machine);
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return -1;
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}
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}
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bool arch_callee_saved_reg(unsigned char reg)
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{
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switch (reg) {
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case CFI_BP:
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case CFI_BX:
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case CFI_R12:
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case CFI_R13:
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case CFI_R14:
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case CFI_R15:
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return true;
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case CFI_AX:
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case CFI_CX:
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case CFI_DX:
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case CFI_SI:
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case CFI_DI:
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case CFI_SP:
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case CFI_R8:
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case CFI_R9:
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case CFI_R10:
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case CFI_R11:
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case CFI_RA:
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default:
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return false;
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}
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}
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unsigned long arch_dest_reloc_offset(int addend)
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{
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return addend + 4;
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}
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unsigned long arch_jump_destination(struct instruction *insn)
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{
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return insn->offset + insn->len + insn->immediate;
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}
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bool arch_pc_relative_reloc(struct reloc *reloc)
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{
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/*
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* All relocation types where P (the address of the target)
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* is included in the computation.
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*/
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switch (reloc_type(reloc)) {
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case R_X86_64_PC8:
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case R_X86_64_PC16:
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case R_X86_64_PC32:
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case R_X86_64_PC64:
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case R_X86_64_PLT32:
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case R_X86_64_GOTPC32:
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case R_X86_64_GOTPCREL:
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return true;
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default:
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break;
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}
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return false;
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}
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#define ADD_OP(op) \
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if (!(op = calloc(1, sizeof(*op)))) \
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return -1; \
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else for (*ops_list = op, ops_list = &op->next; op; op = NULL)
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/*
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* Helpers to decode ModRM/SIB:
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*
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* r/m| AX CX DX BX | SP | BP | SI DI |
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* | R8 R9 R10 R11 | R12 | R13 | R14 R15 |
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* Mod+----------------+-----+-----+---------+
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* 00 | [r/m] |[SIB]|[IP+]| [r/m] |
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* 01 | [r/m + d8] |[S+d]| [r/m + d8] |
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* 10 | [r/m + d32] |[S+D]| [r/m + d32] |
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* 11 | r/ m |
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*/
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#define mod_is_mem() (modrm_mod != 3)
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#define mod_is_reg() (modrm_mod == 3)
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#define is_RIP() ((modrm_rm & 7) == CFI_BP && modrm_mod == 0)
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#define have_SIB() ((modrm_rm & 7) == CFI_SP && mod_is_mem())
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#define rm_is(reg) (have_SIB() ? \
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sib_base == (reg) && sib_index == CFI_SP : \
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modrm_rm == (reg))
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#define rm_is_mem(reg) (mod_is_mem() && !is_RIP() && rm_is(reg))
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#define rm_is_reg(reg) (mod_is_reg() && modrm_rm == (reg))
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static bool has_notrack_prefix(struct insn *insn)
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{
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int i;
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for (i = 0; i < insn->prefixes.nbytes; i++) {
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if (insn->prefixes.bytes[i] == 0x3e)
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return true;
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}
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return false;
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}
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int arch_decode_instruction(struct objtool_file *file, const struct section *sec,
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unsigned long offset, unsigned int maxlen,
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struct instruction *insn)
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{
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struct stack_op **ops_list = &insn->stack_ops;
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const struct elf *elf = file->elf;
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struct insn ins;
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int x86_64, ret;
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unsigned char op1, op2, op3, prefix,
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rex = 0, rex_b = 0, rex_r = 0, rex_w = 0, rex_x = 0,
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modrm = 0, modrm_mod = 0, modrm_rm = 0, modrm_reg = 0,
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sib = 0, /* sib_scale = 0, */ sib_index = 0, sib_base = 0;
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struct stack_op *op = NULL;
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struct symbol *sym;
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u64 imm;
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x86_64 = is_x86_64(elf);
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if (x86_64 == -1)
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return -1;
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ret = insn_decode(&ins, sec->data->d_buf + offset, maxlen,
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x86_64 ? INSN_MODE_64 : INSN_MODE_32);
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if (ret < 0) {
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WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
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return -1;
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}
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insn->len = ins.length;
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insn->type = INSN_OTHER;
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if (ins.vex_prefix.nbytes)
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return 0;
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prefix = ins.prefixes.bytes[0];
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op1 = ins.opcode.bytes[0];
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op2 = ins.opcode.bytes[1];
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op3 = ins.opcode.bytes[2];
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if (ins.rex_prefix.nbytes) {
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rex = ins.rex_prefix.bytes[0];
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rex_w = X86_REX_W(rex) >> 3;
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rex_r = X86_REX_R(rex) >> 2;
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rex_x = X86_REX_X(rex) >> 1;
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rex_b = X86_REX_B(rex);
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}
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if (ins.modrm.nbytes) {
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modrm = ins.modrm.bytes[0];
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modrm_mod = X86_MODRM_MOD(modrm);
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modrm_reg = X86_MODRM_REG(modrm) + 8*rex_r;
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modrm_rm = X86_MODRM_RM(modrm) + 8*rex_b;
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}
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if (ins.sib.nbytes) {
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sib = ins.sib.bytes[0];
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/* sib_scale = X86_SIB_SCALE(sib); */
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sib_index = X86_SIB_INDEX(sib) + 8*rex_x;
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sib_base = X86_SIB_BASE(sib) + 8*rex_b;
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}
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switch (op1) {
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case 0x1:
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case 0x29:
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if (rex_w && rm_is_reg(CFI_SP)) {
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/* add/sub reg, %rsp */
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ADD_OP(op) {
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op->src.type = OP_SRC_ADD;
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op->src.reg = modrm_reg;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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}
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}
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break;
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case 0x50 ... 0x57:
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/* push reg */
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ADD_OP(op) {
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op->src.type = OP_SRC_REG;
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op->src.reg = (op1 & 0x7) + 8*rex_b;
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op->dest.type = OP_DEST_PUSH;
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}
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break;
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case 0x58 ... 0x5f:
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/* pop reg */
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ADD_OP(op) {
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op->src.type = OP_SRC_POP;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = (op1 & 0x7) + 8*rex_b;
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}
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break;
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case 0x68:
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case 0x6a:
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/* push immediate */
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ADD_OP(op) {
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op->src.type = OP_SRC_CONST;
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op->dest.type = OP_DEST_PUSH;
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}
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break;
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case 0x70 ... 0x7f:
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insn->type = INSN_JUMP_CONDITIONAL;
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break;
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case 0x80 ... 0x83:
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/*
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* 1000 00sw : mod OP r/m : immediate
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*
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* s - sign extend immediate
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* w - imm8 / imm32
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*
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* OP: 000 ADD 100 AND
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* 001 OR 101 SUB
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* 010 ADC 110 XOR
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* 011 SBB 111 CMP
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*/
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/* 64bit only */
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if (!rex_w)
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break;
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/* %rsp target only */
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if (!rm_is_reg(CFI_SP))
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break;
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imm = ins.immediate.value;
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if (op1 & 2) { /* sign extend */
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if (op1 & 1) { /* imm32 */
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imm <<= 32;
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imm = (s64)imm >> 32;
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} else { /* imm8 */
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imm <<= 56;
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imm = (s64)imm >> 56;
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}
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}
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switch (modrm_reg & 7) {
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case 5:
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imm = -imm;
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fallthrough;
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case 0:
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/* add/sub imm, %rsp */
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ADD_OP(op) {
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op->src.type = OP_SRC_ADD;
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op->src.reg = CFI_SP;
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op->src.offset = imm;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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}
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break;
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case 4:
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/* and imm, %rsp */
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ADD_OP(op) {
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op->src.type = OP_SRC_AND;
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op->src.reg = CFI_SP;
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op->src.offset = ins.immediate.value;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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}
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break;
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default:
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/* WARN ? */
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break;
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}
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break;
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case 0x89:
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if (!rex_w)
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break;
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if (modrm_reg == CFI_SP) {
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if (mod_is_reg()) {
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/* mov %rsp, reg */
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ADD_OP(op) {
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op->src.type = OP_SRC_REG;
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op->src.reg = CFI_SP;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = modrm_rm;
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}
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break;
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} else {
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/* skip RIP relative displacement */
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if (is_RIP())
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break;
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/* skip nontrivial SIB */
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if (have_SIB()) {
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modrm_rm = sib_base;
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if (sib_index != CFI_SP)
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break;
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}
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/* mov %rsp, disp(%reg) */
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ADD_OP(op) {
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op->src.type = OP_SRC_REG;
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op->src.reg = CFI_SP;
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op->dest.type = OP_DEST_REG_INDIRECT;
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op->dest.reg = modrm_rm;
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op->dest.offset = ins.displacement.value;
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}
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break;
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}
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break;
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}
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if (rm_is_reg(CFI_SP)) {
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/* mov reg, %rsp */
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ADD_OP(op) {
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op->src.type = OP_SRC_REG;
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op->src.reg = modrm_reg;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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}
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break;
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}
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fallthrough;
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case 0x88:
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if (!rex_w)
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break;
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if (rm_is_mem(CFI_BP)) {
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/* mov reg, disp(%rbp) */
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ADD_OP(op) {
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op->src.type = OP_SRC_REG;
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op->src.reg = modrm_reg;
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op->dest.type = OP_DEST_REG_INDIRECT;
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op->dest.reg = CFI_BP;
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op->dest.offset = ins.displacement.value;
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}
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break;
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}
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if (rm_is_mem(CFI_SP)) {
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/* mov reg, disp(%rsp) */
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ADD_OP(op) {
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op->src.type = OP_SRC_REG;
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op->src.reg = modrm_reg;
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op->dest.type = OP_DEST_REG_INDIRECT;
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op->dest.reg = CFI_SP;
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op->dest.offset = ins.displacement.value;
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}
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break;
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}
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break;
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case 0x8b:
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if (!rex_w)
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break;
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if (rm_is_mem(CFI_BP)) {
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/* mov disp(%rbp), reg */
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ADD_OP(op) {
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op->src.type = OP_SRC_REG_INDIRECT;
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op->src.reg = CFI_BP;
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op->src.offset = ins.displacement.value;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = modrm_reg;
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}
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break;
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}
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if (rm_is_mem(CFI_SP)) {
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/* mov disp(%rsp), reg */
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ADD_OP(op) {
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op->src.type = OP_SRC_REG_INDIRECT;
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op->src.reg = CFI_SP;
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op->src.offset = ins.displacement.value;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = modrm_reg;
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}
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break;
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}
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break;
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case 0x8d:
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if (mod_is_reg()) {
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WARN("invalid LEA encoding at %s:0x%lx", sec->name, offset);
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break;
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}
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/* skip non 64bit ops */
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if (!rex_w)
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break;
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/* skip RIP relative displacement */
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if (is_RIP())
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break;
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/* skip nontrivial SIB */
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if (have_SIB()) {
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modrm_rm = sib_base;
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if (sib_index != CFI_SP)
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break;
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}
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/* lea disp(%src), %dst */
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ADD_OP(op) {
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op->src.offset = ins.displacement.value;
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if (!op->src.offset) {
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/* lea (%src), %dst */
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op->src.type = OP_SRC_REG;
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} else {
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/* lea disp(%src), %dst */
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op->src.type = OP_SRC_ADD;
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}
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op->src.reg = modrm_rm;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = modrm_reg;
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}
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break;
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case 0x8f:
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/* pop to mem */
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ADD_OP(op) {
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op->src.type = OP_SRC_POP;
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op->dest.type = OP_DEST_MEM;
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}
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break;
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case 0x90:
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insn->type = INSN_NOP;
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break;
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case 0x9c:
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/* pushf */
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ADD_OP(op) {
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op->src.type = OP_SRC_CONST;
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op->dest.type = OP_DEST_PUSHF;
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}
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break;
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case 0x9d:
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/* popf */
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ADD_OP(op) {
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op->src.type = OP_SRC_POPF;
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op->dest.type = OP_DEST_MEM;
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}
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break;
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case 0x0f:
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if (op2 == 0x01) {
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switch (insn_last_prefix_id(&ins)) {
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case INAT_PFX_REPE:
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case INAT_PFX_REPNE:
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if (modrm == 0xca)
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/* eretu/erets */
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insn->type = INSN_CONTEXT_SWITCH;
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break;
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default:
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if (modrm == 0xca)
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insn->type = INSN_CLAC;
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else if (modrm == 0xcb)
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insn->type = INSN_STAC;
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break;
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}
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} else if (op2 >= 0x80 && op2 <= 0x8f) {
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insn->type = INSN_JUMP_CONDITIONAL;
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} else if (op2 == 0x05 || op2 == 0x07 || op2 == 0x34 ||
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op2 == 0x35) {
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/* sysenter, sysret */
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insn->type = INSN_CONTEXT_SWITCH;
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} else if (op2 == 0x0b || op2 == 0xb9) {
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|
|
|
/* ud2 */
|
|
insn->type = INSN_BUG;
|
|
|
|
} else if (op2 == 0x0d || op2 == 0x1f) {
|
|
|
|
/* nopl/nopw */
|
|
insn->type = INSN_NOP;
|
|
|
|
} else if (op2 == 0x1e) {
|
|
|
|
if (prefix == 0xf3 && (modrm == 0xfa || modrm == 0xfb))
|
|
insn->type = INSN_ENDBR;
|
|
|
|
|
|
} else if (op2 == 0x38 && op3 == 0xf8) {
|
|
if (ins.prefixes.nbytes == 1 &&
|
|
ins.prefixes.bytes[0] == 0xf2) {
|
|
/* ENQCMD cannot be used in the kernel. */
|
|
WARN("ENQCMD instruction at %s:%lx", sec->name,
|
|
offset);
|
|
}
|
|
|
|
} else if (op2 == 0xa0 || op2 == 0xa8) {
|
|
|
|
/* push fs/gs */
|
|
ADD_OP(op) {
|
|
op->src.type = OP_SRC_CONST;
|
|
op->dest.type = OP_DEST_PUSH;
|
|
}
|
|
|
|
} else if (op2 == 0xa1 || op2 == 0xa9) {
|
|
|
|
/* pop fs/gs */
|
|
ADD_OP(op) {
|
|
op->src.type = OP_SRC_POP;
|
|
op->dest.type = OP_DEST_MEM;
|
|
}
|
|
}
|
|
|
|
break;
|
|
|
|
case 0xc9:
|
|
/*
|
|
* leave
|
|
*
|
|
* equivalent to:
|
|
* mov bp, sp
|
|
* pop bp
|
|
*/
|
|
ADD_OP(op) {
|
|
op->src.type = OP_SRC_REG;
|
|
op->src.reg = CFI_BP;
|
|
op->dest.type = OP_DEST_REG;
|
|
op->dest.reg = CFI_SP;
|
|
}
|
|
ADD_OP(op) {
|
|
op->src.type = OP_SRC_POP;
|
|
op->dest.type = OP_DEST_REG;
|
|
op->dest.reg = CFI_BP;
|
|
}
|
|
break;
|
|
|
|
case 0xcc:
|
|
/* int3 */
|
|
insn->type = INSN_TRAP;
|
|
break;
|
|
|
|
case 0xe3:
|
|
/* jecxz/jrcxz */
|
|
insn->type = INSN_JUMP_CONDITIONAL;
|
|
break;
|
|
|
|
case 0xe9:
|
|
case 0xeb:
|
|
insn->type = INSN_JUMP_UNCONDITIONAL;
|
|
break;
|
|
|
|
case 0xc2:
|
|
case 0xc3:
|
|
insn->type = INSN_RETURN;
|
|
break;
|
|
|
|
case 0xc7: /* mov imm, r/m */
|
|
if (!opts.noinstr)
|
|
break;
|
|
|
|
if (ins.length == 3+4+4 && !strncmp(sec->name, ".init.text", 10)) {
|
|
struct reloc *immr, *disp;
|
|
struct symbol *func;
|
|
int idx;
|
|
|
|
immr = find_reloc_by_dest(elf, (void *)sec, offset+3);
|
|
disp = find_reloc_by_dest(elf, (void *)sec, offset+7);
|
|
|
|
if (!immr || strcmp(immr->sym->name, "pv_ops"))
|
|
break;
|
|
|
|
idx = (reloc_addend(immr) + 8) / sizeof(void *);
|
|
|
|
func = disp->sym;
|
|
if (disp->sym->type == STT_SECTION)
|
|
func = find_symbol_by_offset(disp->sym->sec, reloc_addend(disp));
|
|
if (!func) {
|
|
WARN("no func for pv_ops[]");
|
|
return -1;
|
|
}
|
|
|
|
objtool_pv_add(file, idx, func);
|
|
}
|
|
|
|
break;
|
|
|
|
case 0xcf: /* iret */
|
|
/*
|
|
* Handle sync_core(), which has an IRET to self.
|
|
* All other IRET are in STT_NONE entry code.
|
|
*/
|
|
sym = find_symbol_containing(sec, offset);
|
|
if (sym && sym->type == STT_FUNC) {
|
|
ADD_OP(op) {
|
|
/* add $40, %rsp */
|
|
op->src.type = OP_SRC_ADD;
|
|
op->src.reg = CFI_SP;
|
|
op->src.offset = 5*8;
|
|
op->dest.type = OP_DEST_REG;
|
|
op->dest.reg = CFI_SP;
|
|
}
|
|
break;
|
|
}
|
|
|
|
fallthrough;
|
|
|
|
case 0xca: /* retf */
|
|
case 0xcb: /* retf */
|
|
insn->type = INSN_CONTEXT_SWITCH;
|
|
break;
|
|
|
|
case 0xe0: /* loopne */
|
|
case 0xe1: /* loope */
|
|
case 0xe2: /* loop */
|
|
insn->type = INSN_JUMP_CONDITIONAL;
|
|
break;
|
|
|
|
case 0xe8:
|
|
insn->type = INSN_CALL;
|
|
/*
|
|
* For the impact on the stack, a CALL behaves like
|
|
* a PUSH of an immediate value (the return address).
|
|
*/
|
|
ADD_OP(op) {
|
|
op->src.type = OP_SRC_CONST;
|
|
op->dest.type = OP_DEST_PUSH;
|
|
}
|
|
break;
|
|
|
|
case 0xfc:
|
|
insn->type = INSN_CLD;
|
|
break;
|
|
|
|
case 0xfd:
|
|
insn->type = INSN_STD;
|
|
break;
|
|
|
|
case 0xff:
|
|
if (modrm_reg == 2 || modrm_reg == 3) {
|
|
|
|
insn->type = INSN_CALL_DYNAMIC;
|
|
if (has_notrack_prefix(&ins))
|
|
WARN("notrack prefix found at %s:0x%lx", sec->name, offset);
|
|
|
|
} else if (modrm_reg == 4) {
|
|
|
|
insn->type = INSN_JUMP_DYNAMIC;
|
|
if (has_notrack_prefix(&ins))
|
|
WARN("notrack prefix found at %s:0x%lx", sec->name, offset);
|
|
|
|
} else if (modrm_reg == 5) {
|
|
|
|
/* jmpf */
|
|
insn->type = INSN_CONTEXT_SWITCH;
|
|
|
|
} else if (modrm_reg == 6) {
|
|
|
|
/* push from mem */
|
|
ADD_OP(op) {
|
|
op->src.type = OP_SRC_CONST;
|
|
op->dest.type = OP_DEST_PUSH;
|
|
}
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
insn->immediate = ins.immediate.nbytes ? ins.immediate.value : 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void arch_initial_func_cfi_state(struct cfi_init_state *state)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < CFI_NUM_REGS; i++) {
|
|
state->regs[i].base = CFI_UNDEFINED;
|
|
state->regs[i].offset = 0;
|
|
}
|
|
|
|
/* initial CFA (call frame address) */
|
|
state->cfa.base = CFI_SP;
|
|
state->cfa.offset = 8;
|
|
|
|
/* initial RA (return address) */
|
|
state->regs[CFI_RA].base = CFI_CFA;
|
|
state->regs[CFI_RA].offset = -8;
|
|
}
|
|
|
|
const char *arch_nop_insn(int len)
|
|
{
|
|
static const char nops[5][5] = {
|
|
{ BYTES_NOP1 },
|
|
{ BYTES_NOP2 },
|
|
{ BYTES_NOP3 },
|
|
{ BYTES_NOP4 },
|
|
{ BYTES_NOP5 },
|
|
};
|
|
|
|
if (len < 1 || len > 5) {
|
|
WARN("invalid NOP size: %d\n", len);
|
|
return NULL;
|
|
}
|
|
|
|
return nops[len-1];
|
|
}
|
|
|
|
#define BYTE_RET 0xC3
|
|
|
|
const char *arch_ret_insn(int len)
|
|
{
|
|
static const char ret[5][5] = {
|
|
{ BYTE_RET },
|
|
{ BYTE_RET, 0xcc },
|
|
{ BYTE_RET, 0xcc, BYTES_NOP1 },
|
|
{ BYTE_RET, 0xcc, BYTES_NOP2 },
|
|
{ BYTE_RET, 0xcc, BYTES_NOP3 },
|
|
};
|
|
|
|
if (len < 1 || len > 5) {
|
|
WARN("invalid RET size: %d\n", len);
|
|
return NULL;
|
|
}
|
|
|
|
return ret[len-1];
|
|
}
|
|
|
|
int arch_decode_hint_reg(u8 sp_reg, int *base)
|
|
{
|
|
switch (sp_reg) {
|
|
case ORC_REG_UNDEFINED:
|
|
*base = CFI_UNDEFINED;
|
|
break;
|
|
case ORC_REG_SP:
|
|
*base = CFI_SP;
|
|
break;
|
|
case ORC_REG_BP:
|
|
*base = CFI_BP;
|
|
break;
|
|
case ORC_REG_SP_INDIRECT:
|
|
*base = CFI_SP_INDIRECT;
|
|
break;
|
|
case ORC_REG_R10:
|
|
*base = CFI_R10;
|
|
break;
|
|
case ORC_REG_R13:
|
|
*base = CFI_R13;
|
|
break;
|
|
case ORC_REG_DI:
|
|
*base = CFI_DI;
|
|
break;
|
|
case ORC_REG_DX:
|
|
*base = CFI_DX;
|
|
break;
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
bool arch_is_retpoline(struct symbol *sym)
|
|
{
|
|
return !strncmp(sym->name, "__x86_indirect_", 15);
|
|
}
|
|
|
|
bool arch_is_rethunk(struct symbol *sym)
|
|
{
|
|
return !strcmp(sym->name, "__x86_return_thunk");
|
|
}
|
|
|
|
bool arch_is_embedded_insn(struct symbol *sym)
|
|
{
|
|
return !strcmp(sym->name, "retbleed_return_thunk") ||
|
|
!strcmp(sym->name, "srso_safe_ret");
|
|
}
|