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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1334 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.113240726@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
173 lines
7.6 KiB
C
173 lines
7.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __SOUND_CS4231_REGS_H
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#define __SOUND_CS4231_REGS_H
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/*
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* Copyright (c) by Jaroslav Kysela <perex@perex.cz>
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* Definitions for CS4231 & InterWave chips & compatible chips registers
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*/
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/* IO ports */
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#define CS4231P(x) (c_d_c_CS4231##x)
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#define c_d_c_CS4231REGSEL 0
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#define c_d_c_CS4231REG 1
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#define c_d_c_CS4231STATUS 2
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#define c_d_c_CS4231PIO 3
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/* codec registers */
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#define CS4231_LEFT_INPUT 0x00 /* left input control */
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#define CS4231_RIGHT_INPUT 0x01 /* right input control */
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#define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
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#define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
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#define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
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#define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
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#define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
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#define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
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#define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
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#define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
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#define CS4231_PIN_CTRL 0x0a /* pin control */
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#define CS4231_TEST_INIT 0x0b /* test and initialization */
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#define CS4231_MISC_INFO 0x0c /* miscellaneous information */
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#define CS4231_LOOPBACK 0x0d /* loopback control */
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#define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
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#define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
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#define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
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#define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */
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#define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
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#define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */
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#define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
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#define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
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#define CS4231_TIMER_LOW 0x14 /* timer low byte */
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#define CS4231_TIMER_HIGH 0x15 /* timer high byte */
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#define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
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#define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */
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#define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
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#define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */
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#define CS4236_EXT_REG 0x17 /* extended register access */
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#define CS4231_IRQ_STATUS 0x18 /* irq status register */
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#define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
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#define CS4231_VERSION 0x19 /* CS4231(A) - version values */
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#define CS4231_MONO_CTRL 0x1a /* mono input/output control */
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#define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
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#define AD1845_PWR_DOWN 0x1b /* power down control */
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#define CS4235_LEFT_MASTER 0x1b /* left master output control */
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#define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
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#define AD1845_CLOCK 0x1d /* crystal clock select and total power down */
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#define CS4235_RIGHT_MASTER 0x1d /* right master output control */
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#define CS4231_REC_UPR_CNT 0x1e /* record upper count */
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#define CS4231_REC_LWR_CNT 0x1f /* record lower count */
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/* definitions for codec register select port - CODECP( REGSEL ) */
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#define CS4231_INIT 0x80 /* CODEC is initializing */
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#define CS4231_MCE 0x40 /* mode change enable */
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#define CS4231_TRD 0x20 /* transfer request disable */
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/* definitions for codec status register - CODECP( STATUS ) */
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#define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
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/* definitions for codec irq status */
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#define CS4231_PLAYBACK_IRQ 0x10
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#define CS4231_RECORD_IRQ 0x20
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#define CS4231_TIMER_IRQ 0x40
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#define CS4231_ALL_IRQS 0x70
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#define CS4231_REC_UNDERRUN 0x08
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#define CS4231_REC_OVERRUN 0x04
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#define CS4231_PLY_OVERRUN 0x02
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#define CS4231_PLY_UNDERRUN 0x01
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/* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
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#define CS4231_ENABLE_MIC_GAIN 0x20
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#define CS4231_MIXS_LINE 0x00
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#define CS4231_MIXS_AUX1 0x40
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#define CS4231_MIXS_MIC 0x80
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#define CS4231_MIXS_ALL 0xc0
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/* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
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#define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
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#define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
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#define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
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#define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
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#define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
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#define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
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#define CS4231_STEREO 0x10 /* stereo mode */
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/* bits 3-1 define frequency divisor */
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#define CS4231_XTAL1 0x00 /* 24.576 crystal */
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#define CS4231_XTAL2 0x01 /* 16.9344 crystal */
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/* definitions for interface control register - CS4231_IFACE_CTRL */
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#define CS4231_RECORD_PIO 0x80 /* record PIO enable */
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#define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
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#define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
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#define CS4231_AUTOCALIB 0x08 /* auto calibrate */
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#define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
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#define CS4231_RECORD_ENABLE 0x02 /* record enable */
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#define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
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/* definitions for pin control register - CS4231_PIN_CTRL */
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#define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
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#define CS4231_XCTL1 0x40 /* external control #1 */
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#define CS4231_XCTL0 0x80 /* external control #0 */
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/* definitions for test and init register - CS4231_TEST_INIT */
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#define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
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#define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
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/* definitions for misc control register - CS4231_MISC_INFO */
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#define CS4231_MODE2 0x40 /* MODE 2 */
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#define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
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#define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
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/* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
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#define CS4231_DACZ 0x01 /* zero DAC when underrun */
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#define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
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#define CS4231_OLB 0x80 /* output level bit */
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/* definitions for Extended Registers - CS4236+ */
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#define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f))
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#define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8)
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#define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */
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#define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */
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#define CS4236_LEFT_MIC 0x28 /* left MIC volume */
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#define CS4236_RIGHT_MIC 0x38 /* right MIC volume */
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#define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */
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#define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */
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#define CS4236_LEFT_FM 0x68 /* left FM volume */
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#define CS4236_RIGHT_FM 0x78 /* right FM volume */
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#define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */
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#define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */
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#define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */
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#define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */
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#define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */
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#define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */
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#define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */
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#define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */
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#define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */
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#define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */
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#define CS4236_VERSION 0x9c /* chip version and ID */
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/* definitions for extended registers - OPTI93X */
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#define OPTi931_AUX_LEFT_INPUT 0x10
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#define OPTi931_AUX_RIGHT_INPUT 0x11
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#define OPTi93X_MIC_LEFT_INPUT 0x14
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#define OPTi93X_MIC_RIGHT_INPUT 0x15
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#define OPTi93X_OUT_LEFT 0x16
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#define OPTi93X_OUT_RIGHT 0x17
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#endif /* __SOUND_CS4231_REGS_H */
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