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4119f0dfbd
Unfortunately, (R) and (W) are valid markups for enumerated lists, as described at: https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#enumerated-lists So, we ned to replace them by: (R) -> (Read) (W) -> (Write) As otherwise, (R) will be displayed as R., with is not what it is desired. There's no need to touch (RO) and (RW). Acked-by: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/6e81ad8064f3ed4f8dc265086fdf1c618043f935.1604042072.git.mchehab+huawei@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
54 lines
2.2 KiB
Plaintext
54 lines
2.2 KiB
Plaintext
What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Enable/disable tracing on this specific trace macrocell.
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Enabling the trace macrocell implies it has been configured
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properly and a sink has been identified for it. The path
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of coresight components linking the source to the sink is
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configured and managed automatically by the coresight framework.
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What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Provides access to the HW event enable register, used in
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conjunction with HW event bank select register.
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What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Gives access to the HW event block select register
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(STMHEBSR) in order to configure up to 256 channels. Used in
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conjunction with "hwevent_enable" register as described above.
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What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Provides access to the stimulus port enable register
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(STMSPER). Used in conjunction with "port_select" described
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below.
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What: /sys/bus/coresight/devices/<memory_map>.stm/port_select
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used to determine which bank of stimulus port bit in
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register STMSPER (see above) apply to.
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What: /sys/bus/coresight/devices/<memory_map>.stm/status
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (Read) List various control and status registers. The specific
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layout and content is driver specific.
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What: /sys/bus/coresight/devices/<memory_map>.stm/traceid
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Holds the trace ID that will appear in the trace stream
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coming from this trace entity.
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