linux/arch/arm/mach-ixp4xx/include/mach/system.h
Mikael Pettersson 74c32e7234 ixp4xx: arch_idle() documentation fixup
The body of the mach-ixp4xx arch_idle() is mysteriously
disabled by an #if 0 .. #endif. Normally one would expect
to find a call to cpu_do_idle() there, but that call is
disabled, even though cpu_do_idle() is implemented for
XScale cores (and ixp4xx is one).

The explanation can be found in the ixp42x developer's manual
which states that the XScale core clock and power management
registers aren't implemented on ixp42x [3.5.2.2].

Also, the disabled code has suffered from bit rot:
- it checks hlt_counter which is obsolete, as that variable
  and all related code now is private to kernel/process.c
- it passes too many parameters to cpu_do_idle()

So this patch:
- adds a comment before the #if 0 to explain why
  cpu_do_idle() mustn't be called on ixp4xx
- removes the obsolete test of hlt_counter and the
  obsolete parameter to cpu_do_idle()

This is purely a documentation fixup and changes no
generated code. Even so, it has been tested on an
ixp420 machine (ds101).

Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
2009-09-21 19:20:03 +02:00

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C

/*
* arch/arm/mach-ixp4xx/include/mach/system.h
*
* Copyright (C) 2002 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <mach/hardware.h>
static inline void arch_idle(void)
{
/* ixp4xx does not implement the XScale PWRMODE register,
* so it must not call cpu_do_idle() here.
*/
#if 0
cpu_do_idle();
#endif
}
static inline void arch_reset(char mode, const char *cmd)
{
if ( 1 && mode == 's') {
/* Jump into ROM at address 0 */
cpu_reset(0);
} else {
/* Use on-chip reset capability */
/* set the "key" register to enable access to
* "timer" and "enable" registers
*/
*IXP4XX_OSWK = IXP4XX_WDT_KEY;
/* write 0 to the timer register for an immediate reset */
*IXP4XX_OSWT = 0;
*IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
}
}