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db3c33c6d3
ATS does not depend on IOV support, so move the code into its own file. This file will also include support for the PRI and PASID capabilities later. Also give ATS its own Kconfig variable to allow selecting it without IOV support. Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
156 lines
3.2 KiB
C
156 lines
3.2 KiB
C
/*
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* drivers/pci/ats.c
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*
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* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
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*
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* PCI Express I/O Virtualization (IOV) support.
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* Address Translation Service 1.0
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*/
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#include <linux/pci-ats.h>
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#include <linux/pci.h>
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#include "pci.h"
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static int ats_alloc_one(struct pci_dev *dev, int ps)
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{
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int pos;
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u16 cap;
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struct pci_ats *ats;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
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if (!pos)
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return -ENODEV;
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ats = kzalloc(sizeof(*ats), GFP_KERNEL);
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if (!ats)
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return -ENOMEM;
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ats->pos = pos;
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ats->stu = ps;
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pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
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ats->qdep = PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
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PCI_ATS_MAX_QDEP;
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dev->ats = ats;
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return 0;
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}
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static void ats_free_one(struct pci_dev *dev)
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{
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kfree(dev->ats);
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dev->ats = NULL;
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}
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/**
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* pci_enable_ats - enable the ATS capability
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* @dev: the PCI device
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* @ps: the IOMMU page shift
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*
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* Returns 0 on success, or negative on failure.
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*/
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int pci_enable_ats(struct pci_dev *dev, int ps)
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{
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int rc;
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u16 ctrl;
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BUG_ON(dev->ats && dev->ats->is_enabled);
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if (ps < PCI_ATS_MIN_STU)
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return -EINVAL;
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if (dev->is_physfn || dev->is_virtfn) {
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struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
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mutex_lock(&pdev->sriov->lock);
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if (pdev->ats)
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rc = pdev->ats->stu == ps ? 0 : -EINVAL;
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else
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rc = ats_alloc_one(pdev, ps);
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if (!rc)
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pdev->ats->ref_cnt++;
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mutex_unlock(&pdev->sriov->lock);
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if (rc)
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return rc;
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}
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if (!dev->is_physfn) {
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rc = ats_alloc_one(dev, ps);
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if (rc)
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return rc;
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}
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ctrl = PCI_ATS_CTRL_ENABLE;
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if (!dev->is_virtfn)
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ctrl |= PCI_ATS_CTRL_STU(ps - PCI_ATS_MIN_STU);
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pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
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dev->ats->is_enabled = 1;
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return 0;
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}
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/**
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* pci_disable_ats - disable the ATS capability
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* @dev: the PCI device
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*/
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void pci_disable_ats(struct pci_dev *dev)
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{
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u16 ctrl;
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BUG_ON(!dev->ats || !dev->ats->is_enabled);
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pci_read_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, &ctrl);
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ctrl &= ~PCI_ATS_CTRL_ENABLE;
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pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
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dev->ats->is_enabled = 0;
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if (dev->is_physfn || dev->is_virtfn) {
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struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
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mutex_lock(&pdev->sriov->lock);
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pdev->ats->ref_cnt--;
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if (!pdev->ats->ref_cnt)
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ats_free_one(pdev);
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mutex_unlock(&pdev->sriov->lock);
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}
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if (!dev->is_physfn)
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ats_free_one(dev);
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}
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/**
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* pci_ats_queue_depth - query the ATS Invalidate Queue Depth
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* @dev: the PCI device
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*
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* Returns the queue depth on success, or negative on failure.
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*
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* The ATS spec uses 0 in the Invalidate Queue Depth field to
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* indicate that the function can accept 32 Invalidate Request.
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* But here we use the `real' values (i.e. 1~32) for the Queue
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* Depth; and 0 indicates the function shares the Queue with
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* other functions (doesn't exclusively own a Queue).
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*/
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int pci_ats_queue_depth(struct pci_dev *dev)
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{
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int pos;
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u16 cap;
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if (dev->is_virtfn)
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return 0;
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if (dev->ats)
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return dev->ats->qdep;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
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if (!pos)
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return -ENODEV;
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pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
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return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
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PCI_ATS_MAX_QDEP;
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}
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