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d9909ebe65
Device drivers should not access MMIO registers through hardcoded platform specific address constants. Instead, we can pass the MMIO token to the spear clock driver in the initialization routine to contain that knowledge in the platform code itself. Ideally, the clock driver would use of_iomap() or similar to get the address, and that can be used later, but for now, this is the minimal change. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
185 lines
4.4 KiB
C
185 lines
4.4 KiB
C
/*
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* arch/arm/mach-spear13xx/spear13xx.c
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*
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* SPEAr13XX machines common source file
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*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <viresh.linux@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) "SPEAr13xx: " fmt
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#include <linux/amba/pl022.h>
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#include <linux/clk.h>
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#include <linux/dw_dmac.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/map.h>
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#include <asm/smp_twd.h>
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#include "generic.h"
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#include <mach/spear.h>
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#include "spear13xx-dma.h"
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/* common dw_dma filter routine to be used by peripherals */
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bool dw_dma_filter(struct dma_chan *chan, void *slave)
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{
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struct dw_dma_slave *dws = (struct dw_dma_slave *)slave;
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if (chan->device->dev == dws->dma_dev) {
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chan->private = slave;
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return true;
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} else {
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return false;
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}
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}
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/* ssp device registration */
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static struct dw_dma_slave ssp_dma_param[] = {
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{
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/* Tx */
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.cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX),
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.cfg_lo = 0,
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.src_master = DMA_MASTER_MEMORY,
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.dst_master = DMA_MASTER_SSP0,
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}, {
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/* Rx */
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.cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX),
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.cfg_lo = 0,
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.src_master = DMA_MASTER_SSP0,
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.dst_master = DMA_MASTER_MEMORY,
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}
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};
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struct pl022_ssp_controller pl022_plat_data = {
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.enable_dma = 1,
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.dma_filter = dw_dma_filter,
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.dma_rx_param = &ssp_dma_param[1],
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.dma_tx_param = &ssp_dma_param[0],
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};
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/* CF device registration */
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struct dw_dma_slave cf_dma_priv = {
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.cfg_hi = 0,
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.cfg_lo = 0,
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.src_master = 0,
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.dst_master = 0,
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};
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/* dmac device registeration */
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struct dw_dma_platform_data dmac_plat_data = {
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.nr_channels = 8,
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.chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
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.chan_priority = CHAN_PRIORITY_DESCENDING,
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.block_size = 4095U,
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.nr_masters = 2,
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.data_width = { 3, 3, 0, 0 },
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};
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void __init spear13xx_l2x0_init(void)
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{
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/*
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* 512KB (64KB/way), 8-way associativity, parity supported
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*
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* FIXME: 9th bit, of Auxillary Controller register must be set
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* for some spear13xx devices for stable L2 operation.
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*
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* Enable Early BRESP, L2 prefetch for Instruction and Data,
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* write alloc and 'Full line of zero' options
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*
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*/
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writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL);
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/*
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* Program following latencies in order to make
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* SPEAr1340 work at 600 MHz
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*/
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writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL);
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writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL);
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l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
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}
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/*
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* Following will create 16MB static virtual/physical mappings
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* PHYSICAL VIRTUAL
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* 0xB3000000 0xFE000000
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* 0xE0000000 0xFD000000
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* 0xEC000000 0xFC000000
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* 0xED000000 0xFB000000
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*/
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struct map_desc spear13xx_io_desc[] __initdata = {
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{
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.virtual = (unsigned long)VA_PERIP_GRP2_BASE,
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.pfn = __phys_to_pfn(PERIP_GRP2_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE
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}, {
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.virtual = (unsigned long)VA_PERIP_GRP1_BASE,
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.pfn = __phys_to_pfn(PERIP_GRP1_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE
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}, {
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.virtual = (unsigned long)VA_A9SM_AND_MPMC_BASE,
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.pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE
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}, {
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.virtual = (unsigned long)VA_L2CC_BASE,
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.pfn = __phys_to_pfn(L2CC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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},
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};
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/* This will create static memory mapping for selected devices */
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void __init spear13xx_map_io(void)
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{
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iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
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}
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static void __init spear13xx_clk_init(void)
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{
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if (of_machine_is_compatible("st,spear1310"))
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spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE);
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else if (of_machine_is_compatible("st,spear1340"))
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spear1340_clk_init(VA_MISC_BASE);
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else
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pr_err("%s: Unknown machine\n", __func__);
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}
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void __init spear13xx_timer_init(void)
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{
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char pclk_name[] = "osc_24m_clk";
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struct clk *gpt_clk, *pclk;
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spear13xx_clk_init();
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/* get the system timer clock */
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gpt_clk = clk_get_sys("gpt0", NULL);
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if (IS_ERR(gpt_clk)) {
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pr_err("%s:couldn't get clk for gpt\n", __func__);
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BUG();
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}
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/* get the suitable parent clock for timer*/
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pclk = clk_get(NULL, pclk_name);
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if (IS_ERR(pclk)) {
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pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
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pclk_name);
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BUG();
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}
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clk_set_parent(gpt_clk, pclk);
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clk_put(gpt_clk);
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clk_put(pclk);
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spear_setup_of_timer();
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twd_local_timer_of_register();
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}
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