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846307185f
The PLL requires a clock frequency in a certain platform-dependent range after the pre-divider. The reference clock for the PLL may change due to changes to it's parent clock. Thus, the frequency may be out of range or unsuited for generating the high speed clock for MIPI DSI. Try to keep the pre-devider small, and set the reference clock close to the upper limit before recalculating the PLL configuration. Use a divider with a power of two for the reference clock as this seems to work best in my tests. Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM + Waveshare 10.1inch HDMI LCD (E) Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20230818-samsung-dsim-v2-3-846603df0e0a@pengutronix.de Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230818-samsung-dsim-v2-3-846603df0e0a@pengutronix.de
126 lines
2.9 KiB
C
126 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2022 Amarula Solutions(India)
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#ifndef __SAMSUNG_DSIM__
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#define __SAMSUNG_DSIM__
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#include <linux/gpio/consumer.h>
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#include <linux/regulator/consumer.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_of.h>
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#include <drm/drm_mipi_dsi.h>
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struct samsung_dsim;
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#define DSIM_STATE_ENABLED BIT(0)
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#define DSIM_STATE_INITIALIZED BIT(1)
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#define DSIM_STATE_CMD_LPM BIT(2)
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#define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
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enum samsung_dsim_type {
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DSIM_TYPE_EXYNOS3250,
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DSIM_TYPE_EXYNOS4210,
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DSIM_TYPE_EXYNOS5410,
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DSIM_TYPE_EXYNOS5422,
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DSIM_TYPE_EXYNOS5433,
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DSIM_TYPE_IMX8MM,
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DSIM_TYPE_IMX8MP,
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DSIM_TYPE_COUNT,
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};
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#define samsung_dsim_hw_is_exynos(hw) \
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((hw) >= DSIM_TYPE_EXYNOS3250 && (hw) <= DSIM_TYPE_EXYNOS5433)
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struct samsung_dsim_transfer {
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struct list_head list;
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struct completion completed;
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int result;
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struct mipi_dsi_packet packet;
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u16 flags;
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u16 tx_done;
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u8 *rx_payload;
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u16 rx_len;
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u16 rx_done;
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};
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struct samsung_dsim_driver_data {
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const unsigned int *reg_ofs;
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unsigned int plltmr_reg;
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unsigned int has_freqband:1;
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unsigned int has_clklane_stop:1;
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unsigned int has_broken_fifoctrl_emptyhdr:1;
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unsigned int num_clks;
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unsigned int min_freq;
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unsigned int max_freq;
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unsigned int wait_for_reset;
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unsigned int num_bits_resol;
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unsigned int pll_p_offset;
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const unsigned int *reg_values;
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unsigned int pll_fin_min;
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unsigned int pll_fin_max;
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u16 m_min;
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u16 m_max;
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};
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struct samsung_dsim_host_ops {
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int (*register_host)(struct samsung_dsim *dsim);
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void (*unregister_host)(struct samsung_dsim *dsim);
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int (*attach)(struct samsung_dsim *dsim, struct mipi_dsi_device *device);
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void (*detach)(struct samsung_dsim *dsim, struct mipi_dsi_device *device);
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irqreturn_t (*te_irq_handler)(struct samsung_dsim *dsim);
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};
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struct samsung_dsim_plat_data {
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enum samsung_dsim_type hw_type;
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const struct samsung_dsim_host_ops *host_ops;
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};
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struct samsung_dsim {
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struct mipi_dsi_host dsi_host;
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struct drm_bridge bridge;
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struct drm_bridge *out_bridge;
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struct device *dev;
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struct drm_display_mode mode;
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void __iomem *reg_base;
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struct phy *phy;
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struct clk **clks;
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struct clk *pll_clk;
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struct regulator_bulk_data supplies[2];
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int irq;
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struct gpio_desc *te_gpio;
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u32 pll_clk_rate;
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u32 burst_clk_rate;
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u32 hs_clock;
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u32 esc_clk_rate;
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u32 lanes;
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u32 mode_flags;
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u32 format;
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bool swap_dn_dp_clk;
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bool swap_dn_dp_data;
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int state;
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struct drm_property *brightness;
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struct completion completed;
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spinlock_t transfer_lock; /* protects transfer_list */
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struct list_head transfer_list;
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const struct samsung_dsim_driver_data *driver_data;
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const struct samsung_dsim_plat_data *plat_data;
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void *priv;
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};
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extern int samsung_dsim_probe(struct platform_device *pdev);
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extern void samsung_dsim_remove(struct platform_device *pdev);
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extern const struct dev_pm_ops samsung_dsim_pm_ops;
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#endif /* __SAMSUNG_DSIM__ */
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